When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale).

Dean Camera 14 years ago
parent 1a4a26271e
commit c15eaa5dae

@ -68,7 +68,7 @@ void USB_Init(
if (!(USB_Options & USB_OPT_MANUAL_PLL))
{
#if defined(USB_SERIES_4_AVR)
PLLFRQ = ((1 << PLLUSB) | (1 << PDIV3) | (1 << PDIV1));
PLLFRQ = (1 << PDIV2);
#endif
}

@ -15,7 +15,8 @@
*
* <b>Changed:</b>
* - Core:
* - None
* - When automatic PLL management mode is enabled on the U4 series AVR8 chips, the PLL is now configured for 48MHz and not
* a divided 96MHz, to lower power consumption and to keep the system within the datasheet specs for 3.3V operation (thanks to Scott Vitale)
* - Library Applications:
* - None
*

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