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353 lines
21 KiB
C
353 lines
21 KiB
C
/***************************************************************************//**
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* @file
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* @brief This file contains the EFR32 radio coexistence interface.
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*******************************************************************************
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* # License
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* <b>Copyright 2020 Silicon Laboratories Inc. www.silabs.com</b>
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*******************************************************************************
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*
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* The licensor of this software is Silicon Laboratories Inc. Your use of this
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* software is governed by the terms of Silicon Labs Master Software License
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* Agreement (MSLA) available at
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* www.silabs.com/about-us/legal/master-software-license-agreement. This
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* software is distributed to you in Source Code format and is governed by the
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* sections of the MSLA applicable to Source Code.
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*
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******************************************************************************/
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#ifndef __COEXISTENCE_HAL_H__
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#define __COEXISTENCE_HAL_H__
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#include "em_device.h"
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#include "em_prs.h"
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#ifdef HAL_CONFIG
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#include "hal-config.h"
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#else
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#include "sl_rail_util_coex_config.h"
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#endif // HAL_CONFIG
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#ifdef TEST_COEX_HAL_CONFIG
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#include "coexistence-hal-config.h"
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#endif //TEST_COEX_HAL_CONFIG
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#include "coexistence.h"
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#include "em_gpio.h"
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#include "em_prs.h"
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#include "gpiointerrupt.h"
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typedef struct COEX_HAL_GpioConfig {
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/** GPIO port */
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uint8_t port;
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/** GPIO pin */
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uint8_t pin;
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/** GPIO interrupt number */
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uint8_t intNo;
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/** GPIO assert polarity */
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bool polarity;
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/** GPIO PWM enabled */
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bool pwmEnabled;
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/** GPIO mode */
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uint8_t mode;
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/** GPIO ISR */
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GPIOINT_IrqCallbackPtr_t isr;
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/** GPIO config */
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COEX_GpioConfig_t config;
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} COEX_HAL_GpioConfig_t;
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void COEX_HAL_Init(void);
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bool COEX_HAL_ConfigRequest(COEX_HAL_GpioConfig_t *gpioConfig);
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bool COEX_HAL_ConfigPwmRequest(COEX_HAL_GpioConfig_t *gpioConfig);
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bool COEX_HAL_ConfigRadioHoldOff(COEX_HAL_GpioConfig_t *gpioConfig);
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bool COEX_HAL_ConfigPriority(COEX_HAL_GpioConfig_t *gpioConfig);
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bool COEX_HAL_ConfigGrant(COEX_HAL_GpioConfig_t *gpioConfig);
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bool COEX_HAL_ConfigDp(uint8_t pulseWidthUs);
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uint8_t COEX_HAL_GetDpPulseWidth(void);
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bool COEX_HAL_SetDpPulseWidth(uint8_t pulseWidthUs);
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#if defined(HAL_COEX_OVERRIDE_GPIO_INPUT) && !defined(SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT)
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#define SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT HAL_COEX_OVERRIDE_GPIO_INPUT
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#endif //defined(HAL_COEX_OVERRIDE_GPIO_INPUT) and !defined(SL_RAIL_UTIL_COEX_OVERRIDE_GPIO_INPUT)
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#if defined(HAL_COEX_DP_TIMER) && !defined(SL_RAIL_UTIL_COEX_DP_TIMER)
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#define SL_RAIL_UTIL_COEX_DP_TIMER HAL_COEX_DP_TIMER
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#endif //defined(HAL_COEX_DP_TIMER) and !defined(SL_RAIL_UTIL_COEX_DP_TIMER)
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#if defined(HAL_COEX_PWM_PRIORITY) && !defined(SL_RAIL_UTIL_COEX_PWM_PRIORITY)
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#define SL_RAIL_UTIL_COEX_PWM_PRIORITY HAL_COEX_PWM_PRIORITY
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#endif //defined(HAL_COEX_PWM_PRIORITY) and !defined(SL_RAIL_UTIL_COEX_PWM_PRIORITY)
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#if defined(HAL_COEX_RETRYRX_ENABLE) && !defined(SL_RAIL_UTIL_COEX_RETRYRX_ENABLE)
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#define SL_RAIL_UTIL_COEX_RETRYRX_ENABLE HAL_COEX_RETRYRX_ENABLE
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#endif //defined(HAL_COEX_RETRYRX_ENABLE) and !defined(SL_RAIL_UTIL_COEX_RETRYRX_ENABLE)
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#if defined(HAL_COEX_MAC_FAIL_THRESHOLD) && !defined(SL_RAIL_UTIL_COEX_MAC_FAIL_THRESHOLD)
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#define SL_RAIL_UTIL_COEX_MAC_FAIL_THRESHOLD HAL_COEX_MAC_FAIL_THRESHOLD
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#endif //defined(HAL_COEX_MAC_FAIL_THRESHOLD) and !defined(SL_RAIL_UTIL_COEX_MAC_FAIL_THRESHOLD)
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#if defined(HAL_COEX_REQ_WINDOW) && !defined(SL_RAIL_UTIL_COEX_REQ_WINDOW)
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#define SL_RAIL_UTIL_COEX_REQ_WINDOW HAL_COEX_REQ_WINDOW
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#endif //defined(HAL_COEX_REQ_WINDOW) and !defined(SL_RAIL_UTIL_COEX_REQ_WINDOW)
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#if defined(HAL_COEX_PWM_DEFAULT_ENABLED) && !defined(SL_RAIL_UTIL_COEX_PWM_DEFAULT_ENABLED)
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#define SL_RAIL_UTIL_COEX_PWM_DEFAULT_ENABLED HAL_COEX_PWM_DEFAULT_ENABLED
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#endif //defined(HAL_COEX_PWM_DEFAULT_ENABLED) and !defined(SL_RAIL_UTIL_COEX_PWM_DEFAULT_ENABLED)
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#if defined(HAL_COEX_TX_ABORT) && !defined(SL_RAIL_UTIL_COEX_TX_ABORT)
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#define SL_RAIL_UTIL_COEX_TX_ABORT HAL_COEX_TX_ABORT
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#endif //defined(HAL_COEX_TX_ABORT) and !defined(SL_RAIL_UTIL_COEX_TX_ABORT)
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#if defined(BSP_COEX_RHO_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_RHO_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_RHO_ASSERT_LEVEL BSP_COEX_RHO_ASSERT_LEVEL
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#endif //defined(BSP_COEX_RHO_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_RHO_ASSERT_LEVEL)
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#if defined(HAL_COEX_REQ_SHARED) && !defined(SL_RAIL_UTIL_COEX_REQ_SHARED)
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#define SL_RAIL_UTIL_COEX_REQ_SHARED HAL_COEX_REQ_SHARED
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#endif //defined(HAL_COEX_REQ_SHARED) and !defined(SL_RAIL_UTIL_COEX_REQ_SHARED)
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#if defined(HAL_COEX_DP_PULSE_WIDTH_US) && !defined(SL_RAIL_UTIL_COEX_DP_PULSE_WIDTH_US)
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#define SL_RAIL_UTIL_COEX_DP_PULSE_WIDTH_US HAL_COEX_DP_PULSE_WIDTH_US
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#endif //defined(HAL_COEX_DP_PULSE_WIDTH_US) and !defined(SL_RAIL_UTIL_COEX_DP_PULSE_WIDTH_US)
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#if defined(BSP_COEX_PRI_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_PRI_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_PRI_ASSERT_LEVEL BSP_COEX_PRI_ASSERT_LEVEL
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#endif //defined(BSP_COEX_PRI_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_PRI_ASSERT_LEVEL)
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#if defined(HAL_COEX_TX_HIPRI) && !defined(SL_RAIL_UTIL_COEX_TX_HIPRI)
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#define SL_RAIL_UTIL_COEX_TX_HIPRI HAL_COEX_TX_HIPRI
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#endif //defined(HAL_COEX_TX_HIPRI) and !defined(SL_RAIL_UTIL_COEX_TX_HIPRI)
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#if defined(BSP_COEX_REQ_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL BSP_COEX_REQ_ASSERT_LEVEL
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#endif //defined(BSP_COEX_REQ_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL)
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#if defined(HAL_COEX_RX_HIPRI) && !defined(SL_RAIL_UTIL_COEX_RX_HIPRI)
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#define SL_RAIL_UTIL_COEX_RX_HIPRI HAL_COEX_RX_HIPRI
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#endif //defined(HAL_COEX_RX_HIPRI) and !defined(SL_RAIL_UTIL_COEX_RX_HIPRI)
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#if defined(BSP_COEX_GNT_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_GNT_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_GNT_ASSERT_LEVEL BSP_COEX_GNT_ASSERT_LEVEL
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#endif //defined(BSP_COEX_GNT_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_GNT_ASSERT_LEVEL)
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#if defined(HAL_COEX_CCA_THRESHOLD) && !defined(SL_RAIL_UTIL_COEX_CCA_THRESHOLD)
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#define SL_RAIL_UTIL_COEX_CCA_THRESHOLD HAL_COEX_CCA_THRESHOLD
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#endif //defined(HAL_COEX_CCA_THRESHOLD) and !defined(SL_RAIL_UTIL_COEX_CCA_THRESHOLD)
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#if defined(HAL_COEX_PWM_REQ_DUTYCYCLE) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_DUTYCYCLE)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_DUTYCYCLE HAL_COEX_PWM_REQ_DUTYCYCLE
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#endif //defined(HAL_COEX_PWM_REQ_DUTYCYCLE) and !defined(SL_RAIL_UTIL_COEX_PWM_REQ_DUTYCYCLE)
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#if defined(HAL_COEX_RETRYRX_HIPRI) && !defined(SL_RAIL_UTIL_COEX_RETRYRX_HIPRI)
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#define SL_RAIL_UTIL_COEX_RETRYRX_HIPRI HAL_COEX_RETRYRX_HIPRI
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#endif //defined(HAL_COEX_RETRYRX_HIPRI) and !defined(SL_RAIL_UTIL_COEX_RETRYRX_HIPRI)
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#if defined(HAL_COEX_RETRYRX_TIMEOUT) && !defined(SL_RAIL_UTIL_COEX_RETRYRX_TIMEOUT)
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#define SL_RAIL_UTIL_COEX_RETRYRX_TIMEOUT HAL_COEX_RETRYRX_TIMEOUT
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#endif //defined(HAL_COEX_RETRYRX_TIMEOUT) and !defined(SL_RAIL_UTIL_COEX_RETRYRX_TIMEOUT)
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#if defined(HAL_COEX_REQ_BACKOFF) && !defined(SL_RAIL_UTIL_COEX_REQ_BACKOFF)
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#define SL_RAIL_UTIL_COEX_REQ_BACKOFF HAL_COEX_REQ_BACKOFF
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#endif //defined(HAL_COEX_REQ_BACKOFF) and !defined(SL_RAIL_UTIL_COEX_REQ_BACKOFF)
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#if defined(HAL_COEX_PRI_SHARED) && !defined(SL_RAIL_UTIL_COEX_PRI_SHARED)
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#define SL_RAIL_UTIL_COEX_PRI_SHARED HAL_COEX_PRI_SHARED
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#endif //defined(HAL_COEX_PRI_SHARED) and !defined(SL_RAIL_UTIL_COEX_PRI_SHARED)
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#if defined(HAL_COEX_DP_ENABLED) && !defined(SL_RAIL_UTIL_COEX_DP_ENABLED)
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#define SL_RAIL_UTIL_COEX_DP_ENABLED HAL_COEX_DP_ENABLED
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#endif //defined(HAL_COEX_DP_ENABLED) and !defined(SL_RAIL_UTIL_COEX_DP_ENABLED)
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#if defined(HAL_COEX_PRIORITY_ESCALATION_ENABLE) && !defined(SL_RAIL_UTIL_COEX_PRIORITY_ESCALATION_ENABLE)
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#define SL_RAIL_UTIL_COEX_PRIORITY_ESCALATION_ENABLE HAL_COEX_PRIORITY_ESCALATION_ENABLE
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#endif //defined(HAL_COEX_PRIORITY_ESCALATION_ENABLE) and !defined(SL_RAIL_UTIL_COEX_PRIORITY_ESCALATION_ENABLE)
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#if defined(HAL_COEX_ACKHOLDOFF) && !defined(SL_RAIL_UTIL_COEX_ACKHOLDOFF)
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#define SL_RAIL_UTIL_COEX_ACKHOLDOFF HAL_COEX_ACKHOLDOFF
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#endif //defined(HAL_COEX_ACKHOLDOFF) and !defined(SL_RAIL_UTIL_COEX_ACKHOLDOFF)
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#if defined(BSP_COEX_PWM_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PIN)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_PIN BSP_COEX_PWM_REQ_PIN
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#endif //defined(BSP_COEX_PWM_REQ_PIN) and !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PIN)
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#if defined(BSP_COEX_PWM_REQ_PORT) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PORT)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_PORT BSP_COEX_PWM_REQ_PORT
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#endif //defined(BSP_COEX_PWM_REQ_PORT) and !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PORT)
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#if defined(HAL_COEX_PWM_REQ_PERIOD) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PERIOD)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_PERIOD HAL_COEX_PWM_REQ_PERIOD
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#endif //defined(HAL_COEX_PWM_REQ_PERIOD) and !defined(SL_RAIL_UTIL_COEX_PWM_REQ_PERIOD)
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#if defined(HAL_COEX_PHY_ENABLED) && !defined(SL_RAIL_UTIL_COEX_PHY_ENABLED)
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#define SL_RAIL_UTIL_COEX_PHY_ENABLED HAL_COEX_PHY_ENABLED
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#endif //defined(HAL_COEX_PHY_ENABLED) and !defined(SL_RAIL_UTIL_COEX_PHY_ENABLED)
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#if defined(BSP_COEX_PWM_REQ_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_ASSERT_LEVEL BSP_COEX_PWM_REQ_ASSERT_LEVEL
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#endif //defined(BSP_COEX_PWM_REQ_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_PWM_REQ_ASSERT_LEVEL)
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#if defined(HAL_COEX_RUNTIME_PHY_SELECT) && !defined(SL_RAIL_UTIL_COEX_RUNTIME_PHY_SELECT)
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#define SL_RAIL_UTIL_COEX_RUNTIME_PHY_SELECT HAL_COEX_RUNTIME_PHY_SELECT
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#endif //defined(HAL_COEX_RUNTIME_PHY_SELECT) and !defined(SL_RAIL_UTIL_COEX_RUNTIME_PHY_SELECT)
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#if defined(BSP_COEX_RX_ACTIVE_PIN) && !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_PIN)
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#define SL_RAIL_UTIL_COEX_RX_ACTIVE_PIN BSP_COEX_RX_ACTIVE_PIN
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#endif //defined(BSP_COEX_RX_ACTIVE_PIN) and !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_PIN)
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#if defined(BSP_COEX_RX_ACTIVE_PORT) && !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT)
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#define SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT BSP_COEX_RX_ACTIVE_PORT
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#endif //defined(BSP_COEX_RX_ACTIVE_PORT) and !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_PORT)
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#if defined(BSP_COEX_RX_ACTIVE_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_RX_ACTIVE_ASSERT_LEVEL BSP_COEX_RX_ACTIVE_ASSERT_LEVEL
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#endif //defined(BSP_COEX_RX_ACTIVE_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_ASSERT_LEVEL)
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#if defined(BSP_COEX_RX_ACTIVE_CHANNEL) && !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL)
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#define SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL BSP_COEX_RX_ACTIVE_CHANNEL
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#endif //defined(BSP_COEX_RX_ACTIVE_CHANNEL) and !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_CHANNEL)
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#if defined(BSP_COEX_RX_ACTIVE_LOC) && !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_LOC)
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#define SL_RAIL_UTIL_COEX_RX_ACTIVE_LOC BSP_COEX_RX_ACTIVE_LOC
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#endif //defined(BSP_COEX_RX_ACTIVE_LOC) and !defined(SL_RAIL_UTIL_COEX_RX_ACTIVE_LOC)
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#if defined(BSP_COEX_PHY_SELECT_PIN) && !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PIN)
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#define SL_RAIL_UTIL_COEX_PHY_SELECT_PIN BSP_COEX_PHY_SELECT_PIN
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#endif //defined(BSP_COEX_PHY_SELECT_PIN) and !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PIN)
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#if defined(BSP_COEX_PHY_SELECT_PORT) && !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PORT)
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#define SL_RAIL_UTIL_COEX_PHY_SELECT_PORT BSP_COEX_PHY_SELECT_PORT
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#endif //defined(BSP_COEX_PHY_SELECT_PORT) and !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PORT)
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#if defined(BSP_COEX_PHY_SELECT_ASSERT_LEVEL) && !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_ASSERT_LEVEL)
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#define SL_RAIL_UTIL_COEX_PHY_SELECT_ASSERT_LEVEL BSP_COEX_PHY_SELECT_ASSERT_LEVEL
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#endif //defined(BSP_COEX_PHY_SELECT_ASSERT_LEVEL) and !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_ASSERT_LEVEL)
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#if defined(HAL_COEX_DEFAULT_PHY_SELECT_TIMEOUT) && !defined(SL_RAIL_UTIL_COEX_DEFAULT_PHY_SELECT_TIMEOUT)
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#define SL_RAIL_UTIL_COEX_DEFAULT_PHY_SELECT_TIMEOUT HAL_COEX_DEFAULT_PHY_SELECT_TIMEOUT
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#endif //defined(HAL_COEX_DEFAULT_PHY_SELECT_TIMEOUT) and !defined(SL_RAIL_UTIL_COEX_DEFAULT_PHY_SELECT_TIMEOUT)
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#if defined(BSP_COEX_GNT_PIN) && !defined(SL_RAIL_UTIL_COEX_GNT_PIN)
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#define SL_RAIL_UTIL_COEX_GNT_PIN BSP_COEX_GNT_PIN
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#endif //defined(BSP_COEX_GNT_PIN) and !defined(SL_RAIL_UTIL_COEX_GNT_PIN)
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#if defined(BSP_COEX_GNT_PORT) && !defined(SL_RAIL_UTIL_COEX_GNT_PORT)
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#define SL_RAIL_UTIL_COEX_GNT_PORT BSP_COEX_GNT_PORT
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#endif //defined(BSP_COEX_GNT_PORT) and !defined(SL_RAIL_UTIL_COEX_GNT_PORT)
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#if defined(BSP_COEX_PRI_PIN) && !defined(SL_RAIL_UTIL_COEX_PRI_PIN)
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#define SL_RAIL_UTIL_COEX_PRI_PIN BSP_COEX_PRI_PIN
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#endif //defined(BSP_COEX_PRI_PIN) and !defined(SL_RAIL_UTIL_COEX_PRI_PIN)
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#if defined(BSP_COEX_PRI_PORT) && !defined(SL_RAIL_UTIL_COEX_PRI_PORT)
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#define SL_RAIL_UTIL_COEX_PRI_PORT BSP_COEX_PRI_PORT
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#endif //defined(BSP_COEX_PRI_PORT) and !defined(SL_RAIL_UTIL_COEX_PRI_PORT)
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#if defined(BSP_COEX_DP_PIN) && !defined(SL_RAIL_UTIL_COEX_DP_OUT_PIN)
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#define SL_RAIL_UTIL_COEX_DP_OUT_PIN BSP_COEX_DP_PIN
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#endif //defined(BSP_COEX_DP_PIN) and !defined(SL_RAIL_UTIL_COEX_DP_OUT_PIN)
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#if defined(BSP_COEX_DP_PORT) && !defined(SL_RAIL_UTIL_COEX_DP_OUT_PORT)
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#define SL_RAIL_UTIL_COEX_DP_OUT_PORT BSP_COEX_DP_PORT
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#endif //defined(BSP_COEX_DP_PORT) and !defined(SL_RAIL_UTIL_COEX_DP_OUT_PORT)
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#if defined(BSP_COEX_DP_LOC) && !defined(SL_RAIL_UTIL_COEX_DP_OUT_LOC)
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#define SL_RAIL_UTIL_COEX_DP_OUT_LOC BSP_COEX_DP_LOC
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#endif //defined(BSP_COEX_DP_LOC) and !defined(SL_RAIL_UTIL_COEX_DP_OUT_LOC)
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#if defined(BSP_COEX_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_REQ_PIN)
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#define SL_RAIL_UTIL_COEX_REQ_PIN BSP_COEX_REQ_PIN
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#endif //defined(BSP_COEX_REQ_PIN) and !defined(SL_RAIL_UTIL_COEX_REQ_PIN)
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#if defined(BSP_COEX_REQ_PORT) && !defined(SL_RAIL_UTIL_COEX_REQ_PORT)
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#define SL_RAIL_UTIL_COEX_REQ_PORT BSP_COEX_REQ_PORT
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#endif //defined(BSP_COEX_REQ_PORT) and !defined(SL_RAIL_UTIL_COEX_REQ_PORT)
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#if defined(BSP_COEX_DP_REQUEST_INV_CHANNEL) && !defined(SL_RAIL_UTIL_COEX_DP_REQUEST_INV_CHANNEL)
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#define SL_RAIL_UTIL_COEX_DP_REQUEST_INV_CHANNEL BSP_COEX_DP_REQUEST_INV_CHANNEL
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#endif //defined(BSP_COEX_DP_REQUEST_INV_CHANNEL) and !defined(SL_RAIL_UTIL_COEX_DP_REQUEST_INV_CHANNEL)
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#if defined(BSP_COEX_DP_CHANNEL) && !defined(SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL)
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#define SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL BSP_COEX_DP_CHANNEL
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#endif //defined(BSP_COEX_DP_CHANNEL) and !defined(SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL)
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#if defined(BSP_COEX_DP_CC0_PIN) && !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PIN)
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#define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PIN BSP_COEX_DP_CC0_PIN
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#endif //defined(BSP_COEX_DP_CC0_PIN) and !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PIN)
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#if defined(BSP_COEX_DP_CC0_PORT) && !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PORT)
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#define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PORT BSP_COEX_DP_CC0_PORT
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#endif //defined(BSP_COEX_DP_CC0_PORT) and !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_PORT)
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#if defined(BSP_COEX_DP_CC0_LOC) && !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_LOC)
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#define SL_RAIL_UTIL_COEX_DP_TIMER_CC0_LOC BSP_COEX_DP_CC0_LOC
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#endif //defined(BSP_COEX_DP_CC0_LOC) and !defined(SL_RAIL_UTIL_COEX_DP_TIMER_CC0_LOC)
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#define WRAP_PRS_ASYNC(ch) (((ch) + PRS_ASYNC_CHAN_COUNT) % PRS_ASYNC_CHAN_COUNT)
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#if defined(SL_RAIL_UTIL_COEX_GNT_PIN) && !defined(SL_RAIL_UTIL_COEX_GNT_INTNO)
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#define SL_RAIL_UTIL_COEX_GNT_INTNO SL_RAIL_UTIL_COEX_GNT_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_GNT_PIN) && !defined(SL_RAIL_UTIL_COEX_GNT_INTNO)
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#if defined(SL_RAIL_UTIL_COEX_PRI_PIN) && !defined(SL_RAIL_UTIL_COEX_PRI_INTNO)
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#define SL_RAIL_UTIL_COEX_PRI_INTNO SL_RAIL_UTIL_COEX_PRI_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_PRI_PIN) && !defined(SL_RAIL_UTIL_COEX_PRI_INTNO)
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#if defined(SL_RAIL_UTIL_COEX_PWM_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_INTNO)
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#define SL_RAIL_UTIL_COEX_PWM_REQ_INTNO SL_RAIL_UTIL_COEX_PWM_REQ_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_PWM_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_PWM_REQ_INTNO)
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#if defined(SL_RAIL_UTIL_COEX_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_REQ_INTNO)
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#define SL_RAIL_UTIL_COEX_REQ_INTNO SL_RAIL_UTIL_COEX_REQ_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_REQ_PIN) && !defined(SL_RAIL_UTIL_COEX_REQ_INTNO)
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#if defined(SL_RAIL_UTIL_COEX_RHO_PIN) && !defined(SL_RAIL_UTIL_COEX_RHO_INTNO)
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#define SL_RAIL_UTIL_COEX_RHO_INTNO SL_RAIL_UTIL_COEX_RHO_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_RHO_PIN) && !defined(SL_RAIL_UTIL_COEX_RHO_INTNO)
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#if defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PIN) && !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_INTNO)
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#define SL_RAIL_UTIL_COEX_PHY_SELECT_INTNO SL_RAIL_UTIL_COEX_PHY_SELECT_PIN
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#endif //defined(SL_RAIL_UTIL_COEX_PHY_SELECT_PIN) && !defined(SL_RAIL_UTIL_COEX_PHY_SELECT_INTNO)
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#if defined(PER_REG_BLOCK_SET_OFFSET)
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#define COEX_HAL_GPIO_ADDR(port, polarity) ((uint32_t)&GPIO->P[port].DOUT \
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+ (polarity \
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? PER_REG_BLOCK_SET_OFFSET \
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: PER_REG_BLOCK_CLR_OFFSET))
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#elif defined(PER_BITSET_MEM_BASE)
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#define COEX_HAL_GPIO_ADDR(port, polarity) ((uint32_t)&GPIO->P[port].DOUT \
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- PER_MEM_BASE + (polarity \
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? PER_BITSET_MEM_BASE \
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: PER_BITCLR_MEM_BASE))
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#endif //defined(PER_REG_BLOCK_SET_OFFSET) || defined(PER_BITSET_MEM_BASE)
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#if defined(SL_RAIL_UTIL_COEX_REQ_PORT) && defined(COEX_HAL_GPIO_ADDR)
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#define COEX_HAL_FAST_REQUEST 1
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#define COEX_HAL_ReadGpio(port, \
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pin, \
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polarity) \
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(!!GPIO_PinInGet((GPIO_Port_TypeDef)port, pin) \
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== !!polarity)
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#define COEX_HAL_SetGpio(port, \
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pin, \
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polarity) \
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do { \
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*((volatile uint32_t *)COEX_HAL_GPIO_ADDR(port, polarity)) = 1U << pin; \
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} while (0)
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#define COEX_HAL_ReadRequest() \
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COEX_HAL_ReadGpio(SL_RAIL_UTIL_COEX_REQ_PORT, \
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SL_RAIL_UTIL_COEX_REQ_PIN, \
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SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL)
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#ifdef SL_RAIL_UTIL_COEX_PWM_REQ_PORT
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#define COEX_HAL_SetPwmRequest() \
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COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_PWM_REQ_PORT, \
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SL_RAIL_UTIL_COEX_PWM_REQ_PIN, \
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SL_RAIL_UTIL_COEX_PWM_REQ_ASSERT_LEVEL)
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#define COEX_HAL_ClearPwmRequest() \
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COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_PWM_REQ_PORT, \
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SL_RAIL_UTIL_COEX_PWM_REQ_PIN, \
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!SL_RAIL_UTIL_COEX_PWM_REQ_ASSERT_LEVEL)
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#else //!SL_RAIL_UTIL_COEX_PWM_REQ_PORT
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#define COEX_HAL_SetPwmRequest() //no-op
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#define COEX_HAL_ClearPwmRequest() //no-op
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#endif //SL_RAIL_UTIL_COEX_PWM_REQ_PORT
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#define COEX_HAL_SetRequest() \
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COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_REQ_PORT, \
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SL_RAIL_UTIL_COEX_REQ_PIN, \
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SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL)
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#define COEX_HAL_ClearRequest() \
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COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_REQ_PORT, \
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SL_RAIL_UTIL_COEX_REQ_PIN, \
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!SL_RAIL_UTIL_COEX_REQ_ASSERT_LEVEL)
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#if defined(SL_RAIL_UTIL_COEX_PRI_PORT)
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#define COEX_HAL_SetPriority() \
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COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_PRI_PORT, \
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SL_RAIL_UTIL_COEX_PRI_PIN, \
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SL_RAIL_UTIL_COEX_PRI_ASSERT_LEVEL)
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#define COEX_HAL_ClearPriority() \
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|
COEX_HAL_SetGpio(SL_RAIL_UTIL_COEX_PRI_PORT, \
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SL_RAIL_UTIL_COEX_PRI_PIN, \
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!SL_RAIL_UTIL_COEX_PRI_ASSERT_LEVEL)
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#elif defined(SL_RAIL_UTIL_COEX_DP_OUT_PORT) //!defined(SL_RAIL_UTIL_COEX_PRI_PORT)
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#ifdef _SILICON_LABS_32B_SERIES_1
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#define COEX_HAL_DP_PRS_ON (PRS_CH_CTRL_ORPREV | PRS_CH_CTRL_INV)
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|
#define COEX_HAL_DP_PRS_OFF (PRS_CH_CTRL_INV)
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|
#define COEX_HAL_CONFIG_DP_PRS(ch, ctrl) \
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|
do { \
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PRS->CH[ch].CTRL = (PRS->CH[ch].CTRL & ~COEX_HAL_DP_PRS_ON) | ctrl; \
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|
} while (0)
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|
#define COEX_HAL_GET_DP_PRS(ch) ((PRS->CH[ch].CTRL & PRS_CH_CTRL_ORPREV) == PRS_CH_CTRL_ORPREV)
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#else //!_SILICON_LABS_32B_SERIES_1
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#define COEX_HAL_DP_PRS_ON (prsLogic_A_NOR_B)
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|
#define COEX_HAL_DP_PRS_OFF (prsLogic_NOT_A)
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|
#define COEX_HAL_CONFIG_DP_PRS(ch, logic) \
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|
do { \
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|
PRS->ASYNC_CH[ch].CTRL = (PRS->ASYNC_CH[ch].CTRL & ~_PRS_ASYNC_CH_CTRL_FNSEL_MASK) \
|
|
| ((uint32_t)logic << _PRS_ASYNC_CH_CTRL_FNSEL_SHIFT); \
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} while (0)
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#define COEX_HAL_GET_DP_PRS(ch) ((PRS->ASYNC_CH[ch].CTRL & _PRS_ASYNC_CH_CTRL_FNSEL_MASK) == COEX_HAL_DP_PRS_ON)
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#endif //_SILICON_LABS_32B_SERIES_1
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#define COEX_HAL_SetPriority() COEX_HAL_CONFIG_DP_PRS(WRAP_PRS_ASYNC(SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL - 1), COEX_HAL_DP_PRS_ON)
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#define COEX_HAL_ClearPriority() COEX_HAL_CONFIG_DP_PRS(WRAP_PRS_ASYNC(SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL - 1), COEX_HAL_DP_PRS_OFF)
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#define COEX_HAL_GetPriority() COEX_HAL_GET_DP_PRS(WRAP_PRS_ASYNC(SL_RAIL_UTIL_COEX_DP_OUT_CHANNEL - 1))
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#else //!(defined(SL_RAIL_UTIL_COEX_PRI_PORT))
|
|
#define COEX_HAL_SetPriority() //no-op
|
|
#define COEX_HAL_ClearPriority() //no-op
|
|
#endif //defined(SL_RAIL_UTIL_COEX_PRI_PORT)
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#endif //defined(SL_RAIL_UTIL_COEX_REQ_PORT) && defined(COEX_HAL_GPIO_ADDR)
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#endif // __COEXISTENCE_HAL_H__
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