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148 lines
12 KiB
C
148 lines
12 KiB
C
/**************************************************************************//**
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* @file
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* @brief BGM22 ULFRCO register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2021 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifndef BGM22_ULFRCO_H
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#define BGM22_ULFRCO_H
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#define ULFRCO_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup BGM22_ULFRCO ULFRCO
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* @{
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* @brief BGM22 ULFRCO Register Declaration.
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*****************************************************************************/
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/** ULFRCO Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP version */
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uint32_t RESERVED0[1U]; /**< Reserved for future use */
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__IM uint32_t STATUS; /**< Status Register */
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uint32_t RESERVED1[2U]; /**< Reserved for future use */
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__IOM uint32_t IF; /**< Interrupt Flag Register */
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__IOM uint32_t IEN; /**< Interrupt Enable Register */
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uint32_t RESERVED2[1017U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP version */
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uint32_t RESERVED3[1U]; /**< Reserved for future use */
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__IM uint32_t STATUS_SET; /**< Status Register */
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uint32_t RESERVED4[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
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uint32_t RESERVED5[1017U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP version */
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uint32_t RESERVED6[1U]; /**< Reserved for future use */
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__IM uint32_t STATUS_CLR; /**< Status Register */
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uint32_t RESERVED7[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
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uint32_t RESERVED8[1017U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP version */
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uint32_t RESERVED9[1U]; /**< Reserved for future use */
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__IM uint32_t STATUS_TGL; /**< Status Register */
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uint32_t RESERVED10[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
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} ULFRCO_TypeDef;
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/** @} End of group BGM22_ULFRCO */
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/**************************************************************************//**
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* @addtogroup BGM22_ULFRCO
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* @{
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* @defgroup BGM22_ULFRCO_BitFields ULFRCO Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for ULFRCO IPVERSION */
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#define _ULFRCO_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IPVERSION */
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#define _ULFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for ULFRCO_IPVERSION */
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#define _ULFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for ULFRCO_IPVERSION */
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#define _ULFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for ULFRCO_IPVERSION */
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#define _ULFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IPVERSION */
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#define ULFRCO_IPVERSION_IPVERSION_DEFAULT (_ULFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IPVERSION */
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/* Bit fields for ULFRCO STATUS */
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#define _ULFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_STATUS */
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#define _ULFRCO_STATUS_MASK 0x00010001UL /**< Mask for ULFRCO_STATUS */
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#define ULFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
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#define _ULFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
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#define _ULFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
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#define _ULFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
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#define ULFRCO_STATUS_RDY_DEFAULT (_ULFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
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#define ULFRCO_STATUS_ENS (0x1UL << 16) /**< Enable Status */
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#define _ULFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for ULFRCO_ENS */
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#define _ULFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for ULFRCO_ENS */
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#define _ULFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_STATUS */
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#define ULFRCO_STATUS_ENS_DEFAULT (_ULFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for ULFRCO_STATUS */
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/* Bit fields for ULFRCO IF */
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#define _ULFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IF */
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#define _ULFRCO_IF_MASK 0x00000007UL /**< Mask for ULFRCO_IF */
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#define ULFRCO_IF_RDY (0x1UL << 0) /**< Ready Interrupt Flag */
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#define _ULFRCO_IF_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
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#define _ULFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
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#define _ULFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
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#define ULFRCO_IF_RDY_DEFAULT (_ULFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IF */
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#define ULFRCO_IF_POSEDGE (0x1UL << 1) /**< Positive Edge Interrupt Flag */
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#define _ULFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
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#define _ULFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
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#define _ULFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
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#define ULFRCO_IF_POSEDGE_DEFAULT (_ULFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IF */
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#define ULFRCO_IF_NEGEDGE (0x1UL << 2) /**< Negative Edge Interrupt Flag */
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#define _ULFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
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#define _ULFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
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#define _ULFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IF */
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#define ULFRCO_IF_NEGEDGE_DEFAULT (_ULFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IF */
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/* Bit fields for ULFRCO IEN */
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#define _ULFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for ULFRCO_IEN */
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#define _ULFRCO_IEN_MASK 0x00000007UL /**< Mask for ULFRCO_IEN */
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#define ULFRCO_IEN_RDY (0x1UL << 0) /**< Enable Ready Interrupt */
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#define _ULFRCO_IEN_RDY_SHIFT 0 /**< Shift value for ULFRCO_RDY */
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#define _ULFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for ULFRCO_RDY */
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#define _ULFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
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#define ULFRCO_IEN_RDY_DEFAULT (_ULFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for ULFRCO_IEN */
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#define ULFRCO_IEN_POSEDGE (0x1UL << 1) /**< Enable Positive Edge Interrupt */
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#define _ULFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for ULFRCO_POSEDGE */
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#define _ULFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for ULFRCO_POSEDGE */
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#define _ULFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
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#define ULFRCO_IEN_POSEDGE_DEFAULT (_ULFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for ULFRCO_IEN */
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#define ULFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Enable Negative Edge Interrupt */
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#define _ULFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for ULFRCO_NEGEDGE */
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#define _ULFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for ULFRCO_NEGEDGE */
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#define _ULFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for ULFRCO_IEN */
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#define ULFRCO_IEN_NEGEDGE_DEFAULT (_ULFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for ULFRCO_IEN */
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/** @} End of group BGM22_ULFRCO_BitFields */
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/** @} End of group BGM22_ULFRCO */
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/** @} End of group Parts */
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#endif /* BGM22_ULFRCO_H */
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