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364 lines
39 KiB
C
364 lines
39 KiB
C
/**************************************************************************//**
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* @file
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* @brief BGM22 PDM register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2021 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifndef BGM22_PDM_H
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#define BGM22_PDM_H
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#define PDM_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup BGM22_PDM PDM
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* @{
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* @brief BGM22 PDM Register Declaration.
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*****************************************************************************/
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/** PDM Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP Version ID */
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__IOM uint32_t EN; /**< PDM Module enable Register */
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__IOM uint32_t CTRL; /**< PDM Core Control Register */
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__IOM uint32_t CMD; /**< PDM Core Command Register */
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__IM uint32_t STATUS; /**< PDM Status register */
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__IOM uint32_t CFG0; /**< PDM Core Configuration Register0 */
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__IOM uint32_t CFG1; /**< PDM Core Configuration Register1 */
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uint32_t RESERVED0[1U]; /**< Reserved for future use */
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__IM uint32_t RXDATA; /**< PDM Received Data Register */
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uint32_t RESERVED1[7U]; /**< Reserved for future use */
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__IOM uint32_t IF; /**< Interrupt Flag Register */
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__IOM uint32_t IEN; /**< Interrupt Flag Register */
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uint32_t RESERVED2[6U]; /**< Reserved for future use */
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__IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
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uint32_t RESERVED3[999U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP Version ID */
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__IOM uint32_t EN_SET; /**< PDM Module enable Register */
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__IOM uint32_t CTRL_SET; /**< PDM Core Control Register */
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__IOM uint32_t CMD_SET; /**< PDM Core Command Register */
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__IM uint32_t STATUS_SET; /**< PDM Status register */
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__IOM uint32_t CFG0_SET; /**< PDM Core Configuration Register0 */
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__IOM uint32_t CFG1_SET; /**< PDM Core Configuration Register1 */
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uint32_t RESERVED4[1U]; /**< Reserved for future use */
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__IM uint32_t RXDATA_SET; /**< PDM Received Data Register */
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uint32_t RESERVED5[7U]; /**< Reserved for future use */
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__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_SET; /**< Interrupt Flag Register */
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uint32_t RESERVED6[6U]; /**< Reserved for future use */
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__IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */
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uint32_t RESERVED7[999U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP Version ID */
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__IOM uint32_t EN_CLR; /**< PDM Module enable Register */
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__IOM uint32_t CTRL_CLR; /**< PDM Core Control Register */
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__IOM uint32_t CMD_CLR; /**< PDM Core Command Register */
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__IM uint32_t STATUS_CLR; /**< PDM Status register */
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__IOM uint32_t CFG0_CLR; /**< PDM Core Configuration Register0 */
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__IOM uint32_t CFG1_CLR; /**< PDM Core Configuration Register1 */
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uint32_t RESERVED8[1U]; /**< Reserved for future use */
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__IM uint32_t RXDATA_CLR; /**< PDM Received Data Register */
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uint32_t RESERVED9[7U]; /**< Reserved for future use */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_CLR; /**< Interrupt Flag Register */
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uint32_t RESERVED10[6U]; /**< Reserved for future use */
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__IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */
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uint32_t RESERVED11[999U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP Version ID */
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__IOM uint32_t EN_TGL; /**< PDM Module enable Register */
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__IOM uint32_t CTRL_TGL; /**< PDM Core Control Register */
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__IOM uint32_t CMD_TGL; /**< PDM Core Command Register */
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__IM uint32_t STATUS_TGL; /**< PDM Status register */
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__IOM uint32_t CFG0_TGL; /**< PDM Core Configuration Register0 */
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__IOM uint32_t CFG1_TGL; /**< PDM Core Configuration Register1 */
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uint32_t RESERVED12[1U]; /**< Reserved for future use */
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__IM uint32_t RXDATA_TGL; /**< PDM Received Data Register */
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uint32_t RESERVED13[7U]; /**< Reserved for future use */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_TGL; /**< Interrupt Flag Register */
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uint32_t RESERVED14[6U]; /**< Reserved for future use */
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__IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */
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} PDM_TypeDef;
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/** @} End of group BGM22_PDM */
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/**************************************************************************//**
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* @addtogroup BGM22_PDM
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* @{
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* @defgroup BGM22_PDM_BitFields PDM Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for PDM IPVERSION */
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#define _PDM_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for PDM_IPVERSION */
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#define _PDM_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PDM_IPVERSION */
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#define _PDM_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PDM_IPVERSION */
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#define _PDM_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_IPVERSION */
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#define _PDM_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IPVERSION */
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#define PDM_IPVERSION_IPVERSION_DEFAULT (_PDM_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IPVERSION */
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/* Bit fields for PDM EN */
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#define _PDM_EN_RESETVALUE 0x00000000UL /**< Default value for PDM_EN */
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#define _PDM_EN_MASK 0x00000001UL /**< Mask for PDM_EN */
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#define PDM_EN_EN (0x1UL << 0) /**< PDM enable */
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#define _PDM_EN_EN_SHIFT 0 /**< Shift value for PDM_EN */
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#define _PDM_EN_EN_MASK 0x1UL /**< Bit mask for PDM_EN */
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#define _PDM_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_EN */
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#define _PDM_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_EN */
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#define _PDM_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for PDM_EN */
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#define PDM_EN_EN_DEFAULT (_PDM_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_EN */
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#define PDM_EN_EN_DISABLE (_PDM_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for PDM_EN */
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#define PDM_EN_EN_ENABLE (_PDM_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for PDM_EN */
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/* Bit fields for PDM CTRL */
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#define _PDM_CTRL_RESETVALUE 0x00000000UL /**< Default value for PDM_CTRL */
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#define _PDM_CTRL_MASK 0x000FFF1FUL /**< Mask for PDM_CTRL */
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#define _PDM_CTRL_GAIN_SHIFT 0 /**< Shift value for PDM_GAIN */
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#define _PDM_CTRL_GAIN_MASK 0x1FUL /**< Bit mask for PDM_GAIN */
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#define _PDM_CTRL_GAIN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */
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#define PDM_CTRL_GAIN_DEFAULT (_PDM_CTRL_GAIN_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CTRL */
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#define _PDM_CTRL_DSR_SHIFT 8 /**< Shift value for PDM_DSR */
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#define _PDM_CTRL_DSR_MASK 0xFFF00UL /**< Bit mask for PDM_DSR */
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#define _PDM_CTRL_DSR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CTRL */
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#define PDM_CTRL_DSR_DEFAULT (_PDM_CTRL_DSR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CTRL */
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/* Bit fields for PDM CMD */
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#define _PDM_CMD_RESETVALUE 0x00000000UL /**< Default value for PDM_CMD */
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#define _PDM_CMD_MASK 0x00010111UL /**< Mask for PDM_CMD */
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#define PDM_CMD_START (0x1UL << 0) /**< Start DCF */
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#define _PDM_CMD_START_SHIFT 0 /**< Shift value for PDM_START */
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#define _PDM_CMD_START_MASK 0x1UL /**< Bit mask for PDM_START */
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#define _PDM_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */
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#define PDM_CMD_START_DEFAULT (_PDM_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CMD */
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#define PDM_CMD_STOP (0x1UL << 4) /**< Stop DCF */
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#define _PDM_CMD_STOP_SHIFT 4 /**< Shift value for PDM_STOP */
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#define _PDM_CMD_STOP_MASK 0x10UL /**< Bit mask for PDM_STOP */
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#define _PDM_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */
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#define PDM_CMD_STOP_DEFAULT (_PDM_CMD_STOP_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CMD */
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#define PDM_CMD_CLEAR (0x1UL << 8) /**< Clear DCF */
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#define _PDM_CMD_CLEAR_SHIFT 8 /**< Shift value for PDM_CLEAR */
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#define _PDM_CMD_CLEAR_MASK 0x100UL /**< Bit mask for PDM_CLEAR */
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#define _PDM_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */
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#define PDM_CMD_CLEAR_DEFAULT (_PDM_CMD_CLEAR_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CMD */
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#define PDM_CMD_FIFOFL (0x1UL << 16) /**< FIFO Flush */
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#define _PDM_CMD_FIFOFL_SHIFT 16 /**< Shift value for PDM_FIFOFL */
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#define _PDM_CMD_FIFOFL_MASK 0x10000UL /**< Bit mask for PDM_FIFOFL */
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#define _PDM_CMD_FIFOFL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CMD */
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#define PDM_CMD_FIFOFL_DEFAULT (_PDM_CMD_FIFOFL_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CMD */
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/* Bit fields for PDM STATUS */
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#define _PDM_STATUS_RESETVALUE 0x00000020UL /**< Default value for PDM_STATUS */
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#define _PDM_STATUS_MASK 0x00000731UL /**< Mask for PDM_STATUS */
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#define PDM_STATUS_ACT (0x1UL << 0) /**< PDM is active */
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#define _PDM_STATUS_ACT_SHIFT 0 /**< Shift value for PDM_ACT */
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#define _PDM_STATUS_ACT_MASK 0x1UL /**< Bit mask for PDM_ACT */
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#define _PDM_STATUS_ACT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_ACT_DEFAULT (_PDM_STATUS_ACT_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_FULL (0x1UL << 4) /**< FIFO FULL Status */
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#define _PDM_STATUS_FULL_SHIFT 4 /**< Shift value for PDM_FULL */
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#define _PDM_STATUS_FULL_MASK 0x10UL /**< Bit mask for PDM_FULL */
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#define _PDM_STATUS_FULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_FULL_DEFAULT (_PDM_STATUS_FULL_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_EMPTY (0x1UL << 5) /**< FIFO EMPTY Status */
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#define _PDM_STATUS_EMPTY_SHIFT 5 /**< Shift value for PDM_EMPTY */
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#define _PDM_STATUS_EMPTY_MASK 0x20UL /**< Bit mask for PDM_EMPTY */
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#define _PDM_STATUS_EMPTY_DEFAULT 0x00000001UL /**< Mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_EMPTY_DEFAULT (_PDM_STATUS_EMPTY_DEFAULT << 5) /**< Shifted mode DEFAULT for PDM_STATUS */
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#define _PDM_STATUS_FIFOCNT_SHIFT 8 /**< Shift value for PDM_FIFOCNT */
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#define _PDM_STATUS_FIFOCNT_MASK 0x700UL /**< Bit mask for PDM_FIFOCNT */
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#define _PDM_STATUS_FIFOCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_STATUS */
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#define PDM_STATUS_FIFOCNT_DEFAULT (_PDM_STATUS_FIFOCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_STATUS */
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/* Bit fields for PDM CFG0 */
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#define _PDM_CFG0_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG0 */
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#define _PDM_CFG0_MASK 0x03013713UL /**< Mask for PDM_CFG0 */
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#define _PDM_CFG0_FORDER_SHIFT 0 /**< Shift value for PDM_FORDER */
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#define _PDM_CFG0_FORDER_MASK 0x3UL /**< Bit mask for PDM_FORDER */
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#define _PDM_CFG0_FORDER_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_FORDER_SECOND 0x00000000UL /**< Mode SECOND for PDM_CFG0 */
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#define _PDM_CFG0_FORDER_THIRD 0x00000001UL /**< Mode THIRD for PDM_CFG0 */
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#define _PDM_CFG0_FORDER_FOURTH 0x00000002UL /**< Mode FOURTH for PDM_CFG0 */
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#define _PDM_CFG0_FORDER_FIFTH 0x00000003UL /**< Mode FIFTH for PDM_CFG0 */
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#define PDM_CFG0_FORDER_DEFAULT (_PDM_CFG0_FORDER_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_FORDER_SECOND (_PDM_CFG0_FORDER_SECOND << 0) /**< Shifted mode SECOND for PDM_CFG0 */
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#define PDM_CFG0_FORDER_THIRD (_PDM_CFG0_FORDER_THIRD << 0) /**< Shifted mode THIRD for PDM_CFG0 */
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#define PDM_CFG0_FORDER_FOURTH (_PDM_CFG0_FORDER_FOURTH << 0) /**< Shifted mode FOURTH for PDM_CFG0 */
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#define PDM_CFG0_FORDER_FIFTH (_PDM_CFG0_FORDER_FIFTH << 0) /**< Shifted mode FIFTH for PDM_CFG0 */
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#define PDM_CFG0_NUMCH (0x1UL << 4) /**< Number of Channels */
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#define _PDM_CFG0_NUMCH_SHIFT 4 /**< Shift value for PDM_NUMCH */
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#define _PDM_CFG0_NUMCH_MASK 0x10UL /**< Bit mask for PDM_NUMCH */
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#define _PDM_CFG0_NUMCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_NUMCH_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */
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#define _PDM_CFG0_NUMCH_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */
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#define PDM_CFG0_NUMCH_DEFAULT (_PDM_CFG0_NUMCH_DEFAULT << 4) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_NUMCH_ONE (_PDM_CFG0_NUMCH_ONE << 4) /**< Shifted mode ONE for PDM_CFG0 */
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#define PDM_CFG0_NUMCH_TWO (_PDM_CFG0_NUMCH_TWO << 4) /**< Shifted mode TWO for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_SHIFT 8 /**< Shift value for PDM_DATAFORMAT */
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#define _PDM_CFG0_DATAFORMAT_MASK 0x700UL /**< Bit mask for PDM_DATAFORMAT */
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#define _PDM_CFG0_DATAFORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_RIGHT16 0x00000000UL /**< Mode RIGHT16 for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_DOUBLE16 0x00000001UL /**< Mode DOUBLE16 for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_RIGHT24 0x00000002UL /**< Mode RIGHT24 for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_FULL32BIT 0x00000003UL /**< Mode FULL32BIT for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_LEFT16 0x00000004UL /**< Mode LEFT16 for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_LEFT24 0x00000005UL /**< Mode LEFT24 for PDM_CFG0 */
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#define _PDM_CFG0_DATAFORMAT_RAW32BIT 0x00000006UL /**< Mode RAW32BIT for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_DEFAULT (_PDM_CFG0_DATAFORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_RIGHT16 (_PDM_CFG0_DATAFORMAT_RIGHT16 << 8) /**< Shifted mode RIGHT16 for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_DOUBLE16 (_PDM_CFG0_DATAFORMAT_DOUBLE16 << 8) /**< Shifted mode DOUBLE16 for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_RIGHT24 (_PDM_CFG0_DATAFORMAT_RIGHT24 << 8) /**< Shifted mode RIGHT24 for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_FULL32BIT (_PDM_CFG0_DATAFORMAT_FULL32BIT << 8) /**< Shifted mode FULL32BIT for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_LEFT16 (_PDM_CFG0_DATAFORMAT_LEFT16 << 8) /**< Shifted mode LEFT16 for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_LEFT24 (_PDM_CFG0_DATAFORMAT_LEFT24 << 8) /**< Shifted mode LEFT24 for PDM_CFG0 */
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#define PDM_CFG0_DATAFORMAT_RAW32BIT (_PDM_CFG0_DATAFORMAT_RAW32BIT << 8) /**< Shifted mode RAW32BIT for PDM_CFG0 */
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#define _PDM_CFG0_FIFODVL_SHIFT 12 /**< Shift value for PDM_FIFODVL */
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#define _PDM_CFG0_FIFODVL_MASK 0x3000UL /**< Bit mask for PDM_FIFODVL */
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#define _PDM_CFG0_FIFODVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_FIFODVL_ONE 0x00000000UL /**< Mode ONE for PDM_CFG0 */
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#define _PDM_CFG0_FIFODVL_TWO 0x00000001UL /**< Mode TWO for PDM_CFG0 */
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#define _PDM_CFG0_FIFODVL_THREE 0x00000002UL /**< Mode THREE for PDM_CFG0 */
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#define _PDM_CFG0_FIFODVL_FOUR 0x00000003UL /**< Mode FOUR for PDM_CFG0 */
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#define PDM_CFG0_FIFODVL_DEFAULT (_PDM_CFG0_FIFODVL_DEFAULT << 12) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_FIFODVL_ONE (_PDM_CFG0_FIFODVL_ONE << 12) /**< Shifted mode ONE for PDM_CFG0 */
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#define PDM_CFG0_FIFODVL_TWO (_PDM_CFG0_FIFODVL_TWO << 12) /**< Shifted mode TWO for PDM_CFG0 */
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#define PDM_CFG0_FIFODVL_THREE (_PDM_CFG0_FIFODVL_THREE << 12) /**< Shifted mode THREE for PDM_CFG0 */
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#define PDM_CFG0_FIFODVL_FOUR (_PDM_CFG0_FIFODVL_FOUR << 12) /**< Shifted mode FOUR for PDM_CFG0 */
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#define PDM_CFG0_STEREOMODECH01 (0x1UL << 16) /**< Stereo mode CH01 */
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#define _PDM_CFG0_STEREOMODECH01_SHIFT 16 /**< Shift value for PDM_STEREOMODECH01 */
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#define _PDM_CFG0_STEREOMODECH01_MASK 0x10000UL /**< Bit mask for PDM_STEREOMODECH01 */
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#define _PDM_CFG0_STEREOMODECH01_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_STEREOMODECH01_DISABLE 0x00000000UL /**< Mode DISABLE for PDM_CFG0 */
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#define _PDM_CFG0_STEREOMODECH01_CH01ENABLE 0x00000001UL /**< Mode CH01ENABLE for PDM_CFG0 */
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#define PDM_CFG0_STEREOMODECH01_DEFAULT (_PDM_CFG0_STEREOMODECH01_DEFAULT << 16) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_STEREOMODECH01_DISABLE (_PDM_CFG0_STEREOMODECH01_DISABLE << 16) /**< Shifted mode DISABLE for PDM_CFG0 */
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#define PDM_CFG0_STEREOMODECH01_CH01ENABLE (_PDM_CFG0_STEREOMODECH01_CH01ENABLE << 16) /**< Shifted mode CH01ENABLE for PDM_CFG0 */
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#define PDM_CFG0_CH0CLKPOL (0x1UL << 24) /**< CH0 CLK Polarity */
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#define _PDM_CFG0_CH0CLKPOL_SHIFT 24 /**< Shift value for PDM_CH0CLKPOL */
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#define _PDM_CFG0_CH0CLKPOL_MASK 0x1000000UL /**< Bit mask for PDM_CH0CLKPOL */
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#define _PDM_CFG0_CH0CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_CH0CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */
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#define _PDM_CFG0_CH0CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */
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#define PDM_CFG0_CH0CLKPOL_DEFAULT (_PDM_CFG0_CH0CLKPOL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_CH0CLKPOL_NORMAL (_PDM_CFG0_CH0CLKPOL_NORMAL << 24) /**< Shifted mode NORMAL for PDM_CFG0 */
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#define PDM_CFG0_CH0CLKPOL_INVERT (_PDM_CFG0_CH0CLKPOL_INVERT << 24) /**< Shifted mode INVERT for PDM_CFG0 */
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#define PDM_CFG0_CH1CLKPOL (0x1UL << 25) /**< CH1 CLK Polarity */
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#define _PDM_CFG0_CH1CLKPOL_SHIFT 25 /**< Shift value for PDM_CH1CLKPOL */
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#define _PDM_CFG0_CH1CLKPOL_MASK 0x2000000UL /**< Bit mask for PDM_CH1CLKPOL */
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#define _PDM_CFG0_CH1CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG0 */
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#define _PDM_CFG0_CH1CLKPOL_NORMAL 0x00000000UL /**< Mode NORMAL for PDM_CFG0 */
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#define _PDM_CFG0_CH1CLKPOL_INVERT 0x00000001UL /**< Mode INVERT for PDM_CFG0 */
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#define PDM_CFG0_CH1CLKPOL_DEFAULT (_PDM_CFG0_CH1CLKPOL_DEFAULT << 25) /**< Shifted mode DEFAULT for PDM_CFG0 */
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#define PDM_CFG0_CH1CLKPOL_NORMAL (_PDM_CFG0_CH1CLKPOL_NORMAL << 25) /**< Shifted mode NORMAL for PDM_CFG0 */
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#define PDM_CFG0_CH1CLKPOL_INVERT (_PDM_CFG0_CH1CLKPOL_INVERT << 25) /**< Shifted mode INVERT for PDM_CFG0 */
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/* Bit fields for PDM CFG1 */
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#define _PDM_CFG1_RESETVALUE 0x00000000UL /**< Default value for PDM_CFG1 */
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#define _PDM_CFG1_MASK 0x030003FFUL /**< Mask for PDM_CFG1 */
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#define _PDM_CFG1_PRESC_SHIFT 0 /**< Shift value for PDM_PRESC */
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#define _PDM_CFG1_PRESC_MASK 0x3FFUL /**< Bit mask for PDM_PRESC */
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#define _PDM_CFG1_PRESC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */
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#define PDM_CFG1_PRESC_DEFAULT (_PDM_CFG1_PRESC_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_CFG1 */
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#define _PDM_CFG1_DLYMUXSEL_SHIFT 24 /**< Shift value for PDM_DLYMUXSEL */
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#define _PDM_CFG1_DLYMUXSEL_MASK 0x3000000UL /**< Bit mask for PDM_DLYMUXSEL */
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#define _PDM_CFG1_DLYMUXSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_CFG1 */
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#define PDM_CFG1_DLYMUXSEL_DEFAULT (_PDM_CFG1_DLYMUXSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PDM_CFG1 */
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/* Bit fields for PDM RXDATA */
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#define _PDM_RXDATA_RESETVALUE 0x00000000UL /**< Default value for PDM_RXDATA */
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#define _PDM_RXDATA_MASK 0xFFFFFFFFUL /**< Mask for PDM_RXDATA */
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#define _PDM_RXDATA_RXDATA_SHIFT 0 /**< Shift value for PDM_RXDATA */
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#define _PDM_RXDATA_RXDATA_MASK 0xFFFFFFFFUL /**< Bit mask for PDM_RXDATA */
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#define _PDM_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_RXDATA */
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#define PDM_RXDATA_RXDATA_DEFAULT (_PDM_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_RXDATA */
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/* Bit fields for PDM IF */
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#define _PDM_IF_RESETVALUE 0x00000000UL /**< Default value for PDM_IF */
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#define _PDM_IF_MASK 0x0000000FUL /**< Mask for PDM_IF */
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#define PDM_IF_DV (0x1UL << 0) /**< Data Valid Interrupt Flag */
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#define _PDM_IF_DV_SHIFT 0 /**< Shift value for PDM_DV */
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#define _PDM_IF_DV_MASK 0x1UL /**< Bit mask for PDM_DV */
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#define _PDM_IF_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */
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#define PDM_IF_DV_DEFAULT (_PDM_IF_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IF */
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#define PDM_IF_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Flag */
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#define _PDM_IF_DVL_SHIFT 1 /**< Shift value for PDM_DVL */
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#define _PDM_IF_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */
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#define _PDM_IF_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */
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#define PDM_IF_DVL_DEFAULT (_PDM_IF_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IF */
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#define PDM_IF_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Flag */
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#define _PDM_IF_OF_SHIFT 2 /**< Shift value for PDM_OF */
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#define _PDM_IF_OF_MASK 0x4UL /**< Bit mask for PDM_OF */
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#define _PDM_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */
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#define PDM_IF_OF_DEFAULT (_PDM_IF_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IF */
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#define PDM_IF_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Flag */
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#define _PDM_IF_UF_SHIFT 3 /**< Shift value for PDM_UF */
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#define _PDM_IF_UF_MASK 0x8UL /**< Bit mask for PDM_UF */
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#define _PDM_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IF */
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#define PDM_IF_UF_DEFAULT (_PDM_IF_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IF */
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/* Bit fields for PDM IEN */
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#define _PDM_IEN_RESETVALUE 0x00000000UL /**< Default value for PDM_IEN */
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#define _PDM_IEN_MASK 0x0000000FUL /**< Mask for PDM_IEN */
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#define PDM_IEN_DV (0x1UL << 0) /**< Data Valid Interrupt Enable */
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#define _PDM_IEN_DV_SHIFT 0 /**< Shift value for PDM_DV */
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#define _PDM_IEN_DV_MASK 0x1UL /**< Bit mask for PDM_DV */
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#define _PDM_IEN_DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */
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#define PDM_IEN_DV_DEFAULT (_PDM_IEN_DV_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_IEN */
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#define PDM_IEN_DVL (0x1UL << 1) /**< Data Valid Level Interrupt Enable */
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#define _PDM_IEN_DVL_SHIFT 1 /**< Shift value for PDM_DVL */
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#define _PDM_IEN_DVL_MASK 0x2UL /**< Bit mask for PDM_DVL */
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#define _PDM_IEN_DVL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */
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#define PDM_IEN_DVL_DEFAULT (_PDM_IEN_DVL_DEFAULT << 1) /**< Shifted mode DEFAULT for PDM_IEN */
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#define PDM_IEN_OF (0x1UL << 2) /**< FIFO Overflow Interrupt Enable */
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#define _PDM_IEN_OF_SHIFT 2 /**< Shift value for PDM_OF */
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#define _PDM_IEN_OF_MASK 0x4UL /**< Bit mask for PDM_OF */
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#define _PDM_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */
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#define PDM_IEN_OF_DEFAULT (_PDM_IEN_OF_DEFAULT << 2) /**< Shifted mode DEFAULT for PDM_IEN */
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#define PDM_IEN_UF (0x1UL << 3) /**< FIFO Undeflow Interrupt Enable */
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#define _PDM_IEN_UF_SHIFT 3 /**< Shift value for PDM_UF */
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#define _PDM_IEN_UF_MASK 0x8UL /**< Bit mask for PDM_UF */
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#define _PDM_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_IEN */
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#define PDM_IEN_UF_DEFAULT (_PDM_IEN_UF_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_IEN */
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/* Bit fields for PDM SYNCBUSY */
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#define _PDM_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PDM_SYNCBUSY */
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#define _PDM_SYNCBUSY_MASK 0x00000009UL /**< Mask for PDM_SYNCBUSY */
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#define PDM_SYNCBUSY_SYNCBUSY (0x1UL << 0) /**< sync busy */
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#define _PDM_SYNCBUSY_SYNCBUSY_SHIFT 0 /**< Shift value for PDM_SYNCBUSY */
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#define _PDM_SYNCBUSY_SYNCBUSY_MASK 0x1UL /**< Bit mask for PDM_SYNCBUSY */
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#define _PDM_SYNCBUSY_SYNCBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */
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#define PDM_SYNCBUSY_SYNCBUSY_DEFAULT (_PDM_SYNCBUSY_SYNCBUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */
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#define PDM_SYNCBUSY_FIFOFLBUSY (0x1UL << 3) /**< FIFO Flush Sync busy */
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#define _PDM_SYNCBUSY_FIFOFLBUSY_SHIFT 3 /**< Shift value for PDM_FIFOFLBUSY */
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#define _PDM_SYNCBUSY_FIFOFLBUSY_MASK 0x8UL /**< Bit mask for PDM_FIFOFLBUSY */
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#define _PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PDM_SYNCBUSY */
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#define PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT (_PDM_SYNCBUSY_FIFOFLBUSY_DEFAULT << 3) /**< Shifted mode DEFAULT for PDM_SYNCBUSY */
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/** @} End of group BGM22_PDM_BitFields */
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/** @} End of group BGM22_PDM */
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/** @} End of group Parts */
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#endif /* BGM22_PDM_H */
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