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305 lines
32 KiB
C
305 lines
32 KiB
C
/**************************************************************************//**
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* @file
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* @brief BGM22 LFRCO register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2021 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifndef BGM22_LFRCO_H
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#define BGM22_LFRCO_H
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#define LFRCO_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup BGM22_LFRCO LFRCO
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* @{
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* @brief BGM22 LFRCO Register Declaration.
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*****************************************************************************/
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/** LFRCO Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP version */
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__IOM uint32_t CTRL; /**< Control Register */
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__IM uint32_t STATUS; /**< Status Register */
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uint32_t RESERVED0[2U]; /**< Reserved for future use */
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__IOM uint32_t IF; /**< Interrupt Flag Register */
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__IOM uint32_t IEN; /**< Interrupt Enable Register */
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uint32_t RESERVED1[1U]; /**< Reserved for future use */
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__IOM uint32_t LOCK; /**< Configuration Lock Register */
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__IOM uint32_t CFG; /**< Configuration Register */
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uint32_t RESERVED2[1U]; /**< Reserved for future use */
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__IOM uint32_t NOMCAL; /**< Nominal Calibration Register */
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__IOM uint32_t NOMCALINV; /**< Nominal Calibration Inverted Register */
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__IOM uint32_t CMD; /**< Command Register */
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uint32_t RESERVED3[1010U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP version */
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__IOM uint32_t CTRL_SET; /**< Control Register */
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__IM uint32_t STATUS_SET; /**< Status Register */
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uint32_t RESERVED4[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_SET; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
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uint32_t RESERVED5[1U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_SET; /**< Configuration Lock Register */
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__IOM uint32_t CFG_SET; /**< Configuration Register */
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uint32_t RESERVED6[1U]; /**< Reserved for future use */
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__IOM uint32_t NOMCAL_SET; /**< Nominal Calibration Register */
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__IOM uint32_t NOMCALINV_SET; /**< Nominal Calibration Inverted Register */
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__IOM uint32_t CMD_SET; /**< Command Register */
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uint32_t RESERVED7[1010U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP version */
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__IOM uint32_t CTRL_CLR; /**< Control Register */
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__IM uint32_t STATUS_CLR; /**< Status Register */
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uint32_t RESERVED8[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_CLR; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
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uint32_t RESERVED9[1U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */
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__IOM uint32_t CFG_CLR; /**< Configuration Register */
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uint32_t RESERVED10[1U]; /**< Reserved for future use */
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__IOM uint32_t NOMCAL_CLR; /**< Nominal Calibration Register */
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__IOM uint32_t NOMCALINV_CLR; /**< Nominal Calibration Inverted Register */
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__IOM uint32_t CMD_CLR; /**< Command Register */
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uint32_t RESERVED11[1010U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP version */
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__IOM uint32_t CTRL_TGL; /**< Control Register */
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__IM uint32_t STATUS_TGL; /**< Status Register */
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uint32_t RESERVED12[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_TGL; /**< Interrupt Flag Register */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
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uint32_t RESERVED13[1U]; /**< Reserved for future use */
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__IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */
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__IOM uint32_t CFG_TGL; /**< Configuration Register */
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uint32_t RESERVED14[1U]; /**< Reserved for future use */
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__IOM uint32_t NOMCAL_TGL; /**< Nominal Calibration Register */
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__IOM uint32_t NOMCALINV_TGL; /**< Nominal Calibration Inverted Register */
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__IOM uint32_t CMD_TGL; /**< Command Register */
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} LFRCO_TypeDef;
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/** @} End of group BGM22_LFRCO */
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/**************************************************************************//**
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* @addtogroup BGM22_LFRCO
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* @{
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* @defgroup BGM22_LFRCO_BitFields LFRCO Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for LFRCO IPVERSION */
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#define _LFRCO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFRCO_IPVERSION */
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#define _LFRCO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFRCO_IPVERSION */
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#define _LFRCO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFRCO_IPVERSION */
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#define _LFRCO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFRCO_IPVERSION */
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#define _LFRCO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFRCO_IPVERSION */
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#define LFRCO_IPVERSION_IPVERSION_DEFAULT (_LFRCO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IPVERSION */
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/* Bit fields for LFRCO CTRL */
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#define _LFRCO_CTRL_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CTRL */
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#define _LFRCO_CTRL_MASK 0x00000003UL /**< Mask for LFRCO_CTRL */
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#define LFRCO_CTRL_FORCEEN (0x1UL << 0) /**< Force Enable */
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#define _LFRCO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFRCO_FORCEEN */
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#define _LFRCO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFRCO_FORCEEN */
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#define _LFRCO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */
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#define LFRCO_CTRL_FORCEEN_DEFAULT (_LFRCO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CTRL */
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#define LFRCO_CTRL_DISONDEMAND (0x1UL << 1) /**< Disable On-Demand */
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#define _LFRCO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFRCO_DISONDEMAND */
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#define _LFRCO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFRCO_DISONDEMAND */
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#define _LFRCO_CTRL_DISONDEMAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CTRL */
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#define LFRCO_CTRL_DISONDEMAND_DEFAULT (_LFRCO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_CTRL */
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/* Bit fields for LFRCO STATUS */
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#define _LFRCO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFRCO_STATUS */
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#define _LFRCO_STATUS_MASK 0x80010001UL /**< Mask for LFRCO_STATUS */
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#define LFRCO_STATUS_RDY (0x1UL << 0) /**< Ready Status */
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#define _LFRCO_STATUS_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
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#define _LFRCO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
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#define _LFRCO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
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#define LFRCO_STATUS_RDY_DEFAULT (_LFRCO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_STATUS */
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#define LFRCO_STATUS_ENS (0x1UL << 16) /**< Enabled Status */
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#define _LFRCO_STATUS_ENS_SHIFT 16 /**< Shift value for LFRCO_ENS */
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#define _LFRCO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFRCO_ENS */
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#define _LFRCO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
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#define LFRCO_STATUS_ENS_DEFAULT (_LFRCO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_STATUS */
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#define LFRCO_STATUS_LOCK (0x1UL << 31) /**< Lock Status */
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#define _LFRCO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFRCO_LOCK */
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#define _LFRCO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFRCO_LOCK */
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#define _LFRCO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_STATUS */
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#define _LFRCO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFRCO_STATUS */
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#define _LFRCO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFRCO_STATUS */
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#define LFRCO_STATUS_LOCK_DEFAULT (_LFRCO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFRCO_STATUS */
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#define LFRCO_STATUS_LOCK_UNLOCKED (_LFRCO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFRCO_STATUS */
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#define LFRCO_STATUS_LOCK_LOCKED (_LFRCO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFRCO_STATUS */
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/* Bit fields for LFRCO IF */
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#define _LFRCO_IF_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IF */
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#define _LFRCO_IF_MASK 0x00070707UL /**< Mask for LFRCO_IF */
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#define LFRCO_IF_RDY (0x1UL << 0) /**< Ready Flag */
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#define _LFRCO_IF_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
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#define _LFRCO_IF_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
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#define _LFRCO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_RDY_DEFAULT (_LFRCO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Flag */
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#define _LFRCO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
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#define _LFRCO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
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#define _LFRCO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_POSEDGE_DEFAULT (_LFRCO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Flag */
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#define _LFRCO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
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#define _LFRCO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
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#define _LFRCO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_NEGEDGE_DEFAULT (_LFRCO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TCDONE (0x1UL << 8) /**< Temperature Check Done Flag */
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#define _LFRCO_IF_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */
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#define _LFRCO_IF_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */
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#define _LFRCO_IF_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TCDONE_DEFAULT (_LFRCO_IF_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_CALDONE (0x1UL << 9) /**< Calibration Done Flag */
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#define _LFRCO_IF_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */
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#define _LFRCO_IF_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */
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#define _LFRCO_IF_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_CALDONE_DEFAULT (_LFRCO_IF_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Flag */
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#define _LFRCO_IF_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */
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#define _LFRCO_IF_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */
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#define _LFRCO_IF_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TEMPCHANGE_DEFAULT (_LFRCO_IF_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_SCHEDERR (0x1UL << 16) /**< Scheduling Error Flag */
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#define _LFRCO_IF_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */
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#define _LFRCO_IF_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */
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#define _LFRCO_IF_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_SCHEDERR_DEFAULT (_LFRCO_IF_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Flag */
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#define _LFRCO_IF_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */
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#define _LFRCO_IF_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */
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#define _LFRCO_IF_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_TCOOR_DEFAULT (_LFRCO_IF_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Flag */
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#define _LFRCO_IF_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */
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#define _LFRCO_IF_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */
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#define _LFRCO_IF_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IF */
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#define LFRCO_IF_CALOOR_DEFAULT (_LFRCO_IF_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IF */
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/* Bit fields for LFRCO IEN */
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#define _LFRCO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFRCO_IEN */
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#define _LFRCO_IEN_MASK 0x00070707UL /**< Mask for LFRCO_IEN */
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#define LFRCO_IEN_RDY (0x1UL << 0) /**< Ready Enable */
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#define _LFRCO_IEN_RDY_SHIFT 0 /**< Shift value for LFRCO_RDY */
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#define _LFRCO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFRCO_RDY */
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#define _LFRCO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_RDY_DEFAULT (_LFRCO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Enable */
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#define _LFRCO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFRCO_POSEDGE */
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#define _LFRCO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFRCO_POSEDGE */
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#define _LFRCO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_POSEDGE_DEFAULT (_LFRCO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Enable */
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#define _LFRCO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFRCO_NEGEDGE */
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#define _LFRCO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFRCO_NEGEDGE */
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#define _LFRCO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_NEGEDGE_DEFAULT (_LFRCO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TCDONE (0x1UL << 8) /**< Temperature Check Done Enable */
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#define _LFRCO_IEN_TCDONE_SHIFT 8 /**< Shift value for LFRCO_TCDONE */
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#define _LFRCO_IEN_TCDONE_MASK 0x100UL /**< Bit mask for LFRCO_TCDONE */
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#define _LFRCO_IEN_TCDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TCDONE_DEFAULT (_LFRCO_IEN_TCDONE_DEFAULT << 8) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_CALDONE (0x1UL << 9) /**< Calibration Done Enable */
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#define _LFRCO_IEN_CALDONE_SHIFT 9 /**< Shift value for LFRCO_CALDONE */
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#define _LFRCO_IEN_CALDONE_MASK 0x200UL /**< Bit mask for LFRCO_CALDONE */
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#define _LFRCO_IEN_CALDONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_CALDONE_DEFAULT (_LFRCO_IEN_CALDONE_DEFAULT << 9) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TEMPCHANGE (0x1UL << 10) /**< Temperature Change Enable */
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#define _LFRCO_IEN_TEMPCHANGE_SHIFT 10 /**< Shift value for LFRCO_TEMPCHANGE */
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#define _LFRCO_IEN_TEMPCHANGE_MASK 0x400UL /**< Bit mask for LFRCO_TEMPCHANGE */
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#define _LFRCO_IEN_TEMPCHANGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TEMPCHANGE_DEFAULT (_LFRCO_IEN_TEMPCHANGE_DEFAULT << 10) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_SCHEDERR (0x1UL << 16) /**< Scheduling Error Enable */
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#define _LFRCO_IEN_SCHEDERR_SHIFT 16 /**< Shift value for LFRCO_SCHEDERR */
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#define _LFRCO_IEN_SCHEDERR_MASK 0x10000UL /**< Bit mask for LFRCO_SCHEDERR */
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#define _LFRCO_IEN_SCHEDERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_SCHEDERR_DEFAULT (_LFRCO_IEN_SCHEDERR_DEFAULT << 16) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TCOOR (0x1UL << 17) /**< Temperature Check Out Of Range Enable */
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#define _LFRCO_IEN_TCOOR_SHIFT 17 /**< Shift value for LFRCO_TCOOR */
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#define _LFRCO_IEN_TCOOR_MASK 0x20000UL /**< Bit mask for LFRCO_TCOOR */
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#define _LFRCO_IEN_TCOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_TCOOR_DEFAULT (_LFRCO_IEN_TCOOR_DEFAULT << 17) /**< Shifted mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_CALOOR (0x1UL << 18) /**< Calibration Out Of Range Enable */
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#define _LFRCO_IEN_CALOOR_SHIFT 18 /**< Shift value for LFRCO_CALOOR */
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#define _LFRCO_IEN_CALOOR_MASK 0x40000UL /**< Bit mask for LFRCO_CALOOR */
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#define _LFRCO_IEN_CALOOR_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_IEN */
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#define LFRCO_IEN_CALOOR_DEFAULT (_LFRCO_IEN_CALOOR_DEFAULT << 18) /**< Shifted mode DEFAULT for LFRCO_IEN */
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/* Bit fields for LFRCO LOCK */
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#define _LFRCO_LOCK_RESETVALUE 0x00000000UL /**< Default value for LFRCO_LOCK */
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#define _LFRCO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFRCO_LOCK */
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#define _LFRCO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFRCO_LOCKKEY */
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#define _LFRCO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFRCO_LOCKKEY */
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#define _LFRCO_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_LOCK */
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#define _LFRCO_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for LFRCO_LOCK */
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#define _LFRCO_LOCK_LOCKKEY_UNLOCK 0x00000F93UL /**< Mode UNLOCK for LFRCO_LOCK */
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#define LFRCO_LOCK_LOCKKEY_DEFAULT (_LFRCO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_LOCK */
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#define LFRCO_LOCK_LOCKKEY_LOCK (_LFRCO_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for LFRCO_LOCK */
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#define LFRCO_LOCK_LOCKKEY_UNLOCK (_LFRCO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFRCO_LOCK */
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/* Bit fields for LFRCO CFG */
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#define _LFRCO_CFG_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CFG */
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#define _LFRCO_CFG_MASK 0x00000001UL /**< Mask for LFRCO_CFG */
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#define LFRCO_CFG_HIGHPRECEN (0x1UL << 0) /**< High Precision Enable */
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#define _LFRCO_CFG_HIGHPRECEN_SHIFT 0 /**< Shift value for LFRCO_HIGHPRECEN */
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#define _LFRCO_CFG_HIGHPRECEN_MASK 0x1UL /**< Bit mask for LFRCO_HIGHPRECEN */
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#define _LFRCO_CFG_HIGHPRECEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CFG */
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#define LFRCO_CFG_HIGHPRECEN_DEFAULT (_LFRCO_CFG_HIGHPRECEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CFG */
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/* Bit fields for LFRCO NOMCAL */
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#define _LFRCO_NOMCAL_RESETVALUE 0x0005B8D8UL /**< Default value for LFRCO_NOMCAL */
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#define _LFRCO_NOMCAL_MASK 0x001FFFFFUL /**< Mask for LFRCO_NOMCAL */
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#define _LFRCO_NOMCAL_NOMCALCNT_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNT */
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#define _LFRCO_NOMCAL_NOMCALCNT_MASK 0x1FFFFFUL /**< Bit mask for LFRCO_NOMCALCNT */
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#define _LFRCO_NOMCAL_NOMCALCNT_DEFAULT 0x0005B8D8UL /**< Mode DEFAULT for LFRCO_NOMCAL */
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#define LFRCO_NOMCAL_NOMCALCNT_DEFAULT (_LFRCO_NOMCAL_NOMCALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCAL */
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/* Bit fields for LFRCO NOMCALINV */
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#define _LFRCO_NOMCALINV_RESETVALUE 0x0000597AUL /**< Default value for LFRCO_NOMCALINV */
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#define _LFRCO_NOMCALINV_MASK 0x0001FFFFUL /**< Mask for LFRCO_NOMCALINV */
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#define _LFRCO_NOMCALINV_NOMCALCNTINV_SHIFT 0 /**< Shift value for LFRCO_NOMCALCNTINV */
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#define _LFRCO_NOMCALINV_NOMCALCNTINV_MASK 0x1FFFFUL /**< Bit mask for LFRCO_NOMCALCNTINV */
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#define _LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT 0x0000597AUL /**< Mode DEFAULT for LFRCO_NOMCALINV */
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#define LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT (_LFRCO_NOMCALINV_NOMCALCNTINV_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_NOMCALINV */
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/* Bit fields for LFRCO CMD */
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#define _LFRCO_CMD_RESETVALUE 0x00000000UL /**< Default value for LFRCO_CMD */
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#define _LFRCO_CMD_MASK 0x00000001UL /**< Mask for LFRCO_CMD */
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#define LFRCO_CMD_REDUCETCINT (0x1UL << 0) /**< Reduce Temperature Check Interval */
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#define _LFRCO_CMD_REDUCETCINT_SHIFT 0 /**< Shift value for LFRCO_REDUCETCINT */
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#define _LFRCO_CMD_REDUCETCINT_MASK 0x1UL /**< Bit mask for LFRCO_REDUCETCINT */
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#define _LFRCO_CMD_REDUCETCINT_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFRCO_CMD */
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#define LFRCO_CMD_REDUCETCINT_DEFAULT (_LFRCO_CMD_REDUCETCINT_DEFAULT << 0) /**< Shifted mode DEFAULT for LFRCO_CMD */
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/** @} End of group BGM22_LFRCO_BitFields */
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/** @} End of group BGM22_LFRCO */
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/** @} End of group Parts */
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#endif /* BGM22_LFRCO_H */
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