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738 lines
94 KiB
C
738 lines
94 KiB
C
/**************************************************************************//**
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* @file
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* @brief BGM22 BUFC register and bit field definitions
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******************************************************************************
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* # License
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* <b>Copyright 2021 Silicon Laboratories, Inc. www.silabs.com</b>
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******************************************************************************
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*
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* SPDX-License-Identifier: Zlib
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*
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* The licensor of this software is Silicon Laboratories Inc.
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*
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* This software is provided 'as-is', without any express or implied
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* warranty. In no event will the authors be held liable for any damages
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* arising from the use of this software.
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*
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* Permission is granted to anyone to use this software for any purpose,
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* including commercial applications, and to alter it and redistribute it
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* freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software
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* in a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*****************************************************************************/
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#ifndef BGM22_BUFC_H
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#define BGM22_BUFC_H
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#define BUFC_HAS_SET_CLEAR
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/**************************************************************************//**
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* @addtogroup Parts
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* @{
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******************************************************************************/
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/**************************************************************************//**
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* @defgroup BGM22_BUFC BUFC
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* @{
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* @brief BGM22 BUFC Register Declaration.
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*****************************************************************************/
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/** BUFC BUF Register Group Declaration. */
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typedef struct {
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__IOM uint32_t CTRL; /**< Buffer Control */
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__IOM uint32_t ADDR; /**< Buffer Address */
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__IOM uint32_t WRITEOFFSET; /**< Write Offset */
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__IOM uint32_t READOFFSET; /**< Read Offset */
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uint32_t RESERVED0[1U]; /**< Reserved for future use */
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__IM uint32_t READDATA; /**< Buffer Read Data */
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__IOM uint32_t WRITEDATA; /**< Buffer Write Data */
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__IOM uint32_t XWRITE; /**< Buffer XOR Write */
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__IM uint32_t STATUS; /**< Buffer Status Register */
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__IOM uint32_t THRESHOLDCTRL; /**< Threshold Control */
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__IOM uint32_t CMD; /**< Buffer Command */
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__IOM uint32_t FIFOASYNC; /**< New Register */
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__IM uint32_t READDATA32; /**< Buffer Read Data */
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__IOM uint32_t WRITEDATA32; /**< Buffer Write Data */
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__IOM uint32_t XWRITE32; /**< Buffer XOR Write */
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uint32_t RESERVED1[1U]; /**< Reserved for future use */
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} BUFC_BUF_TypeDef;
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/** BUFC Register Declaration. */
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typedef struct {
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__IM uint32_t IPVERSION; /**< IP Version */
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__IOM uint32_t EN; /**< Enable peripheral clock to this module */
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__IOM uint32_t LPMODE; /**< Low power mode control */
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BUFC_BUF_TypeDef BUF[4U]; /**< Data Buffer */
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uint32_t RESERVED0[2U]; /**< Reserved for future use */
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__IOM uint32_t IF; /**< BUFC Interrupt Flags */
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__IOM uint32_t IEN; /**< Interrupt Enable Register */
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__IOM uint32_t SEQIF; /**< M0P BUFC Interrupt Flags */
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__IOM uint32_t SEQIEN; /**< M0P Interrupt Enable Register */
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uint32_t RESERVED1[1U]; /**< Reserved for future use */
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uint32_t RESERVED2[950U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_SET; /**< IP Version */
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__IOM uint32_t EN_SET; /**< Enable peripheral clock to this module */
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__IOM uint32_t LPMODE_SET; /**< Low power mode control */
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BUFC_BUF_TypeDef BUF_SET[4U]; /**< Data Buffer */
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uint32_t RESERVED3[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_SET; /**< BUFC Interrupt Flags */
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__IOM uint32_t IEN_SET; /**< Interrupt Enable Register */
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__IOM uint32_t SEQIF_SET; /**< M0P BUFC Interrupt Flags */
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__IOM uint32_t SEQIEN_SET; /**< M0P Interrupt Enable Register */
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uint32_t RESERVED4[1U]; /**< Reserved for future use */
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uint32_t RESERVED5[950U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_CLR; /**< IP Version */
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__IOM uint32_t EN_CLR; /**< Enable peripheral clock to this module */
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__IOM uint32_t LPMODE_CLR; /**< Low power mode control */
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BUFC_BUF_TypeDef BUF_CLR[4U]; /**< Data Buffer */
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uint32_t RESERVED6[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_CLR; /**< BUFC Interrupt Flags */
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__IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */
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__IOM uint32_t SEQIF_CLR; /**< M0P BUFC Interrupt Flags */
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__IOM uint32_t SEQIEN_CLR; /**< M0P Interrupt Enable Register */
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uint32_t RESERVED7[1U]; /**< Reserved for future use */
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uint32_t RESERVED8[950U]; /**< Reserved for future use */
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__IM uint32_t IPVERSION_TGL; /**< IP Version */
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__IOM uint32_t EN_TGL; /**< Enable peripheral clock to this module */
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__IOM uint32_t LPMODE_TGL; /**< Low power mode control */
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BUFC_BUF_TypeDef BUF_TGL[4U]; /**< Data Buffer */
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uint32_t RESERVED9[2U]; /**< Reserved for future use */
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__IOM uint32_t IF_TGL; /**< BUFC Interrupt Flags */
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__IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */
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__IOM uint32_t SEQIF_TGL; /**< M0P BUFC Interrupt Flags */
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__IOM uint32_t SEQIEN_TGL; /**< M0P Interrupt Enable Register */
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uint32_t RESERVED10[1U]; /**< Reserved for future use */
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} BUFC_TypeDef;
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/** @} End of group BGM22_BUFC */
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/**************************************************************************//**
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* @addtogroup BGM22_BUFC
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* @{
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* @defgroup BGM22_BUFC_BitFields BUFC Bit Fields
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* @{
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*****************************************************************************/
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/* Bit fields for BUFC IPVERSION */
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#define _BUFC_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for BUFC_IPVERSION */
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#define _BUFC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for BUFC_IPVERSION */
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#define _BUFC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for BUFC_IPVERSION */
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#define _BUFC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_IPVERSION */
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#define _BUFC_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for BUFC_IPVERSION */
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#define BUFC_IPVERSION_IPVERSION_DEFAULT (_BUFC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IPVERSION */
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/* Bit fields for BUFC EN */
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#define _BUFC_EN_RESETVALUE 0x00000000UL /**< Default value for BUFC_EN */
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#define _BUFC_EN_MASK 0x00000001UL /**< Mask for BUFC_EN */
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#define BUFC_EN_EN (0x1UL << 0) /**< Enable peripheral clock to this module */
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#define _BUFC_EN_EN_SHIFT 0 /**< Shift value for BUFC_EN */
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#define _BUFC_EN_EN_MASK 0x1UL /**< Bit mask for BUFC_EN */
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#define _BUFC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_EN */
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#define BUFC_EN_EN_DEFAULT (_BUFC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_EN */
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/* Bit fields for BUFC LPMODE */
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#define _BUFC_LPMODE_RESETVALUE 0x00000000UL /**< Default value for BUFC_LPMODE */
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#define _BUFC_LPMODE_MASK 0x00000003UL /**< Mask for BUFC_LPMODE */
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#define BUFC_LPMODE_LPENBYSEQ (0x1UL << 0) /**< Low power mode enable from M0p sequencer */
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#define _BUFC_LPMODE_LPENBYSEQ_SHIFT 0 /**< Shift value for BUFC_LPENBYSEQ */
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#define _BUFC_LPMODE_LPENBYSEQ_MASK 0x1UL /**< Bit mask for BUFC_LPENBYSEQ */
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#define _BUFC_LPMODE_LPENBYSEQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */
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#define BUFC_LPMODE_LPENBYSEQ_DEFAULT (_BUFC_LPMODE_LPENBYSEQ_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_LPMODE */
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#define BUFC_LPMODE_LPENBYM33 (0x1UL << 1) /**< Low power mode enable from M33 */
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#define _BUFC_LPMODE_LPENBYM33_SHIFT 1 /**< Shift value for BUFC_LPENBYM33 */
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#define _BUFC_LPMODE_LPENBYM33_MASK 0x2UL /**< Bit mask for BUFC_LPENBYM33 */
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#define _BUFC_LPMODE_LPENBYM33_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_LPMODE */
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#define BUFC_LPMODE_LPENBYM33_DEFAULT (_BUFC_LPMODE_LPENBYM33_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_LPMODE */
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/* Bit fields for BUFC BUF_CTRL */
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#define _BUFC_BUF_CTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_MASK 0x00000007UL /**< Mask for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SHIFT 0 /**< Shift value for BUFC_SIZE */
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#define _BUFC_BUF_CTRL_SIZE_MASK 0x7UL /**< Bit mask for BUFC_SIZE */
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#define _BUFC_BUF_CTRL_SIZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE64 0x00000000UL /**< Mode SIZE64 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE128 0x00000001UL /**< Mode SIZE128 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE256 0x00000002UL /**< Mode SIZE256 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE512 0x00000003UL /**< Mode SIZE512 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE1024 0x00000004UL /**< Mode SIZE1024 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE2048 0x00000005UL /**< Mode SIZE2048 for BUFC_BUF_CTRL */
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#define _BUFC_BUF_CTRL_SIZE_SIZE4096 0x00000006UL /**< Mode SIZE4096 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_DEFAULT (_BUFC_BUF_CTRL_SIZE_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE64 (_BUFC_BUF_CTRL_SIZE_SIZE64 << 0) /**< Shifted mode SIZE64 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE128 (_BUFC_BUF_CTRL_SIZE_SIZE128 << 0) /**< Shifted mode SIZE128 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE256 (_BUFC_BUF_CTRL_SIZE_SIZE256 << 0) /**< Shifted mode SIZE256 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE512 (_BUFC_BUF_CTRL_SIZE_SIZE512 << 0) /**< Shifted mode SIZE512 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE1024 (_BUFC_BUF_CTRL_SIZE_SIZE1024 << 0) /**< Shifted mode SIZE1024 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE2048 (_BUFC_BUF_CTRL_SIZE_SIZE2048 << 0) /**< Shifted mode SIZE2048 for BUFC_BUF_CTRL */
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#define BUFC_BUF_CTRL_SIZE_SIZE4096 (_BUFC_BUF_CTRL_SIZE_SIZE4096 << 0) /**< Shifted mode SIZE4096 for BUFC_BUF_CTRL */
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/* Bit fields for BUFC BUF_ADDR */
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#define _BUFC_BUF_ADDR_RESETVALUE 0x20000000UL /**< Default value for BUFC_BUF_ADDR */
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#define _BUFC_BUF_ADDR_MASK 0xFFFFFFFCUL /**< Mask for BUFC_BUF_ADDR */
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#define _BUFC_BUF_ADDR_ADDR_SHIFT 2 /**< Shift value for BUFC_ADDR */
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#define _BUFC_BUF_ADDR_ADDR_MASK 0xFFFFFFFCUL /**< Bit mask for BUFC_ADDR */
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#define _BUFC_BUF_ADDR_ADDR_DEFAULT 0x08000000UL /**< Mode DEFAULT for BUFC_BUF_ADDR */
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#define BUFC_BUF_ADDR_ADDR_DEFAULT (_BUFC_BUF_ADDR_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_BUF_ADDR */
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/* Bit fields for BUFC BUF_WRITEOFFSET */
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#define _BUFC_BUF_WRITEOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEOFFSET */
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#define _BUFC_BUF_WRITEOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_WRITEOFFSET */
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#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_SHIFT 0 /**< Shift value for BUFC_WRITEOFFSET */
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#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_WRITEOFFSET */
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#define _BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEOFFSET */
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#define BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT (_BUFC_BUF_WRITEOFFSET_WRITEOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEOFFSET*/
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/* Bit fields for BUFC BUF_READOFFSET */
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#define _BUFC_BUF_READOFFSET_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READOFFSET */
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#define _BUFC_BUF_READOFFSET_MASK 0x00001FFFUL /**< Mask for BUFC_BUF_READOFFSET */
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#define _BUFC_BUF_READOFFSET_READOFFSET_SHIFT 0 /**< Shift value for BUFC_READOFFSET */
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#define _BUFC_BUF_READOFFSET_READOFFSET_MASK 0x1FFFUL /**< Bit mask for BUFC_READOFFSET */
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#define _BUFC_BUF_READOFFSET_READOFFSET_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READOFFSET */
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#define BUFC_BUF_READOFFSET_READOFFSET_DEFAULT (_BUFC_BUF_READOFFSET_READOFFSET_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READOFFSET*/
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/* Bit fields for BUFC BUF_READDATA */
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#define _BUFC_BUF_READDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA */
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#define _BUFC_BUF_READDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_READDATA */
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#define _BUFC_BUF_READDATA_READDATA_SHIFT 0 /**< Shift value for BUFC_READDATA */
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#define _BUFC_BUF_READDATA_READDATA_MASK 0xFFUL /**< Bit mask for BUFC_READDATA */
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#define _BUFC_BUF_READDATA_READDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA */
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#define BUFC_BUF_READDATA_READDATA_DEFAULT (_BUFC_BUF_READDATA_READDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA */
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/* Bit fields for BUFC BUF_WRITEDATA */
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#define _BUFC_BUF_WRITEDATA_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA */
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#define _BUFC_BUF_WRITEDATA_MASK 0x000000FFUL /**< Mask for BUFC_BUF_WRITEDATA */
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#define _BUFC_BUF_WRITEDATA_WRITEDATA_SHIFT 0 /**< Shift value for BUFC_WRITEDATA */
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#define _BUFC_BUF_WRITEDATA_WRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_WRITEDATA */
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#define _BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA */
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#define BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT (_BUFC_BUF_WRITEDATA_WRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA */
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/* Bit fields for BUFC BUF_XWRITE */
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#define _BUFC_BUF_XWRITE_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE */
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#define _BUFC_BUF_XWRITE_MASK 0x000000FFUL /**< Mask for BUFC_BUF_XWRITE */
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#define _BUFC_BUF_XWRITE_XORWRITEDATA_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA */
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#define _BUFC_BUF_XWRITE_XORWRITEDATA_MASK 0xFFUL /**< Bit mask for BUFC_XORWRITEDATA */
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#define _BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE */
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#define BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT (_BUFC_BUF_XWRITE_XORWRITEDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE */
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/* Bit fields for BUFC BUF_STATUS */
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#define _BUFC_BUF_STATUS_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_STATUS */
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#define _BUFC_BUF_STATUS_MASK 0x01111FFFUL /**< Mask for BUFC_BUF_STATUS */
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#define _BUFC_BUF_STATUS_BYTES_SHIFT 0 /**< Shift value for BUFC_BYTES */
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#define _BUFC_BUF_STATUS_BYTES_MASK 0x1FFFUL /**< Bit mask for BUFC_BYTES */
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#define _BUFC_BUF_STATUS_BYTES_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */
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#define BUFC_BUF_STATUS_BYTES_DEFAULT (_BUFC_BUF_STATUS_BYTES_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */
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#define BUFC_BUF_STATUS_THRESHOLDFLAG (0x1UL << 20) /**< Buffer Threshold Flag */
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#define _BUFC_BUF_STATUS_THRESHOLDFLAG_SHIFT 20 /**< Shift value for BUFC_THRESHOLDFLAG */
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#define _BUFC_BUF_STATUS_THRESHOLDFLAG_MASK 0x100000UL /**< Bit mask for BUFC_THRESHOLDFLAG */
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#define _BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_STATUS */
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#define BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT (_BUFC_BUF_STATUS_THRESHOLDFLAG_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_BUF_STATUS */
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/* Bit fields for BUFC BUF_THRESHOLDCTRL */
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#define _BUFC_BUF_THRESHOLDCTRL_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_THRESHOLDCTRL */
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#define _BUFC_BUF_THRESHOLDCTRL_MASK 0x00002FFFUL /**< Mask for BUFC_BUF_THRESHOLDCTRL */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_SHIFT 0 /**< Shift value for BUFC_THRESHOLD */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_MASK 0xFFFUL /**< Bit mask for BUFC_THRESHOLD */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */
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#define BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLD_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/
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#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE (0x1UL << 13) /**< Buffer Threshold Mode */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_SHIFT 13 /**< Shift value for BUFC_THRESHOLDMODE */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_MASK 0x2000UL /**< Bit mask for BUFC_THRESHOLDMODE */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_THRESHOLDCTRL */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER 0x00000000UL /**< Mode LARGER for BUFC_BUF_THRESHOLDCTRL */
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#define _BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL 0x00000001UL /**< Mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL */
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#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_DEFAULT << 13) /**< Shifted mode DEFAULT for BUFC_BUF_THRESHOLDCTRL*/
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#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LARGER << 13) /**< Shifted mode LARGER for BUFC_BUF_THRESHOLDCTRL*/
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#define BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL (_BUFC_BUF_THRESHOLDCTRL_THRESHOLDMODE_LESSOREQUAL << 13) /**< Shifted mode LESSOREQUAL for BUFC_BUF_THRESHOLDCTRL*/
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/* Bit fields for BUFC BUF_CMD */
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#define _BUFC_BUF_CMD_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_CMD */
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#define _BUFC_BUF_CMD_MASK 0x0000000FUL /**< Mask for BUFC_BUF_CMD */
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#define BUFC_BUF_CMD_CLEAR (0x1UL << 0) /**< Buffer Clear */
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#define _BUFC_BUF_CMD_CLEAR_SHIFT 0 /**< Shift value for BUFC_CLEAR */
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#define _BUFC_BUF_CMD_CLEAR_MASK 0x1UL /**< Bit mask for BUFC_CLEAR */
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#define _BUFC_BUF_CMD_CLEAR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */
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#define BUFC_BUF_CMD_CLEAR_DEFAULT (_BUFC_BUF_CMD_CLEAR_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */
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#define BUFC_BUF_CMD_PREFETCH (0x1UL << 1) /**< Prefetch */
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#define _BUFC_BUF_CMD_PREFETCH_SHIFT 1 /**< Shift value for BUFC_PREFETCH */
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#define _BUFC_BUF_CMD_PREFETCH_MASK 0x2UL /**< Bit mask for BUFC_PREFETCH */
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#define _BUFC_BUF_CMD_PREFETCH_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_CMD */
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#define BUFC_BUF_CMD_PREFETCH_DEFAULT (_BUFC_BUF_CMD_PREFETCH_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_BUF_CMD */
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/* Bit fields for BUFC BUF_FIFOASYNC */
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#define _BUFC_BUF_FIFOASYNC_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_FIFOASYNC */
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#define _BUFC_BUF_FIFOASYNC_MASK 0x00000001UL /**< Mask for BUFC_BUF_FIFOASYNC */
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#define BUFC_BUF_FIFOASYNC_RST (0x1UL << 0) /**< Reset ASYNC */
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#define _BUFC_BUF_FIFOASYNC_RST_SHIFT 0 /**< Shift value for BUFC_RST */
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#define _BUFC_BUF_FIFOASYNC_RST_MASK 0x1UL /**< Bit mask for BUFC_RST */
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#define _BUFC_BUF_FIFOASYNC_RST_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_FIFOASYNC */
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#define BUFC_BUF_FIFOASYNC_RST_DEFAULT (_BUFC_BUF_FIFOASYNC_RST_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_FIFOASYNC */
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/* Bit fields for BUFC BUF_READDATA32 */
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#define _BUFC_BUF_READDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_READDATA32 */
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#define _BUFC_BUF_READDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_READDATA32 */
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#define _BUFC_BUF_READDATA32_READDATA32_SHIFT 0 /**< Shift value for BUFC_READDATA32 */
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#define _BUFC_BUF_READDATA32_READDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_READDATA32 */
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#define _BUFC_BUF_READDATA32_READDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_READDATA32 */
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#define BUFC_BUF_READDATA32_READDATA32_DEFAULT (_BUFC_BUF_READDATA32_READDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_READDATA32*/
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/* Bit fields for BUFC BUF_WRITEDATA32 */
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#define _BUFC_BUF_WRITEDATA32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_WRITEDATA32 */
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#define _BUFC_BUF_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_WRITEDATA32 */
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#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_SHIFT 0 /**< Shift value for BUFC_WRITEDATA32 */
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#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_WRITEDATA32 */
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#define _BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_WRITEDATA32 */
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#define BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT (_BUFC_BUF_WRITEDATA32_WRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_WRITEDATA32*/
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/* Bit fields for BUFC BUF_XWRITE32 */
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#define _BUFC_BUF_XWRITE32_RESETVALUE 0x00000000UL /**< Default value for BUFC_BUF_XWRITE32 */
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#define _BUFC_BUF_XWRITE32_MASK 0xFFFFFFFFUL /**< Mask for BUFC_BUF_XWRITE32 */
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#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_SHIFT 0 /**< Shift value for BUFC_XORWRITEDATA32 */
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#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_MASK 0xFFFFFFFFUL /**< Bit mask for BUFC_XORWRITEDATA32 */
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#define _BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_BUF_XWRITE32 */
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#define BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT (_BUFC_BUF_XWRITE32_XORWRITEDATA32_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_BUF_XWRITE32 */
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/* Bit fields for BUFC IF */
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#define _BUFC_IF_RESETVALUE 0x00000000UL /**< Default value for BUFC_IF */
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#define _BUFC_IF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IF */
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#define BUFC_IF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */
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#define _BUFC_IF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
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#define _BUFC_IF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
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#define _BUFC_IF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0OF_DEFAULT (_BUFC_IF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */
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#define _BUFC_IF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
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#define _BUFC_IF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
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#define _BUFC_IF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0UF_DEFAULT (_BUFC_IF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */
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#define _BUFC_IF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
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#define _BUFC_IF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
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#define _BUFC_IF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0THR_DEFAULT (_BUFC_IF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */
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#define _BUFC_IF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
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#define _BUFC_IF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
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#define _BUFC_IF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0CORR_DEFAULT (_BUFC_IF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */
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#define _BUFC_IF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
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#define _BUFC_IF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
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#define _BUFC_IF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF0NWA_DEFAULT (_BUFC_IF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */
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#define _BUFC_IF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
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#define _BUFC_IF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
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#define _BUFC_IF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1OF_DEFAULT (_BUFC_IF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */
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#define _BUFC_IF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
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#define _BUFC_IF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
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#define _BUFC_IF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1UF_DEFAULT (_BUFC_IF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */
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#define _BUFC_IF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
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#define _BUFC_IF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
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#define _BUFC_IF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1THR_DEFAULT (_BUFC_IF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */
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#define _BUFC_IF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
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#define _BUFC_IF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
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#define _BUFC_IF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1CORR_DEFAULT (_BUFC_IF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */
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#define _BUFC_IF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
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#define _BUFC_IF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
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#define _BUFC_IF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF1NWA_DEFAULT (_BUFC_IF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */
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#define _BUFC_IF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
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#define _BUFC_IF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
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#define _BUFC_IF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2OF_DEFAULT (_BUFC_IF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */
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#define _BUFC_IF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
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#define _BUFC_IF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
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#define _BUFC_IF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2UF_DEFAULT (_BUFC_IF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */
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#define _BUFC_IF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
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#define _BUFC_IF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
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#define _BUFC_IF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2THR_DEFAULT (_BUFC_IF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */
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#define _BUFC_IF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
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#define _BUFC_IF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
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#define _BUFC_IF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2CORR_DEFAULT (_BUFC_IF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */
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#define _BUFC_IF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
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#define _BUFC_IF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
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#define _BUFC_IF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF2NWA_DEFAULT (_BUFC_IF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */
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#define _BUFC_IF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
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#define _BUFC_IF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
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#define _BUFC_IF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3OF_DEFAULT (_BUFC_IF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */
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#define _BUFC_IF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
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#define _BUFC_IF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
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#define _BUFC_IF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3UF_DEFAULT (_BUFC_IF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */
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#define _BUFC_IF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
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#define _BUFC_IF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
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#define _BUFC_IF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3THR_DEFAULT (_BUFC_IF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */
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#define _BUFC_IF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
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#define _BUFC_IF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
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#define _BUFC_IF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3CORR_DEFAULT (_BUFC_IF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */
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#define _BUFC_IF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
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#define _BUFC_IF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
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#define _BUFC_IF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUF3NWA_DEFAULT (_BUFC_IF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUSERROR (0x1UL << 31) /**< Bus Error */
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#define _BUFC_IF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
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#define _BUFC_IF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
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#define _BUFC_IF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IF */
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#define BUFC_IF_BUSERROR_DEFAULT (_BUFC_IF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IF */
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/* Bit fields for BUFC IEN */
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#define _BUFC_IEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_IEN */
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#define _BUFC_IEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_IEN */
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#define BUFC_IEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */
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#define _BUFC_IEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
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#define _BUFC_IEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
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#define _BUFC_IEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0OF_DEFAULT (_BUFC_IEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */
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#define _BUFC_IEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
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#define _BUFC_IEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
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#define _BUFC_IEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0UF_DEFAULT (_BUFC_IEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */
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#define _BUFC_IEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
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#define _BUFC_IEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
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#define _BUFC_IEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0THR_DEFAULT (_BUFC_IEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */
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#define _BUFC_IEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
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#define _BUFC_IEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
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#define _BUFC_IEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0CORR_DEFAULT (_BUFC_IEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */
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#define _BUFC_IEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
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#define _BUFC_IEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
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#define _BUFC_IEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF0NWA_DEFAULT (_BUFC_IEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */
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#define _BUFC_IEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
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#define _BUFC_IEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
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#define _BUFC_IEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1OF_DEFAULT (_BUFC_IEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */
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#define _BUFC_IEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
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#define _BUFC_IEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
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#define _BUFC_IEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1UF_DEFAULT (_BUFC_IEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */
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#define _BUFC_IEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
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#define _BUFC_IEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
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#define _BUFC_IEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1THR_DEFAULT (_BUFC_IEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */
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#define _BUFC_IEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
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#define _BUFC_IEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
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#define _BUFC_IEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1CORR_DEFAULT (_BUFC_IEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */
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#define _BUFC_IEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
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#define _BUFC_IEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
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#define _BUFC_IEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF1NWA_DEFAULT (_BUFC_IEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */
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#define _BUFC_IEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
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#define _BUFC_IEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
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#define _BUFC_IEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF2OF_DEFAULT (_BUFC_IEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */
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#define _BUFC_IEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
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#define _BUFC_IEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
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|
#define _BUFC_IEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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|
#define BUFC_IEN_BUF2UF_DEFAULT (_BUFC_IEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_IEN */
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|
#define BUFC_IEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */
|
|
#define _BUFC_IEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
|
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#define _BUFC_IEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
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|
#define _BUFC_IEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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|
#define BUFC_IEN_BUF2THR_DEFAULT (_BUFC_IEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */
|
|
#define _BUFC_IEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
|
|
#define _BUFC_IEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
|
|
#define _BUFC_IEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF2CORR_DEFAULT (_BUFC_IEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */
|
|
#define _BUFC_IEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
|
|
#define _BUFC_IEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
|
|
#define _BUFC_IEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF2NWA_DEFAULT (_BUFC_IEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_IEN */
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|
#define BUFC_IEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */
|
|
#define _BUFC_IEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
|
|
#define _BUFC_IEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
|
|
#define _BUFC_IEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF3OF_DEFAULT (_BUFC_IEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */
|
|
#define _BUFC_IEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
|
|
#define _BUFC_IEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
|
|
#define _BUFC_IEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
|
|
#define BUFC_IEN_BUF3UF_DEFAULT (_BUFC_IEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */
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#define _BUFC_IEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
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#define _BUFC_IEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
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#define _BUFC_IEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3THR_DEFAULT (_BUFC_IEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */
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#define _BUFC_IEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
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#define _BUFC_IEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
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#define _BUFC_IEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3CORR_DEFAULT (_BUFC_IEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */
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#define _BUFC_IEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
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#define _BUFC_IEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
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#define _BUFC_IEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUF3NWA_DEFAULT (_BUFC_IEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */
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#define _BUFC_IEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
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#define _BUFC_IEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
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#define _BUFC_IEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_IEN */
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#define BUFC_IEN_BUSERROR_DEFAULT (_BUFC_IEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_IEN */
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/* Bit fields for BUFC SEQIF */
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#define _BUFC_SEQIF_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIF */
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#define _BUFC_SEQIF_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0OF (0x1UL << 0) /**< Buffer 0 Overflow */
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#define _BUFC_SEQIF_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
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#define _BUFC_SEQIF_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
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#define _BUFC_SEQIF_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0OF_DEFAULT (_BUFC_SEQIF_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0UF (0x1UL << 1) /**< Buffer 0 Underflow */
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#define _BUFC_SEQIF_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
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#define _BUFC_SEQIF_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
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#define _BUFC_SEQIF_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0UF_DEFAULT (_BUFC_SEQIF_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0THR (0x1UL << 2) /**< Buffer 0 Threshold Event */
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#define _BUFC_SEQIF_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
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#define _BUFC_SEQIF_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
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#define _BUFC_SEQIF_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0THR_DEFAULT (_BUFC_SEQIF_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0CORR (0x1UL << 3) /**< Buffer 0 Corrupt */
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#define _BUFC_SEQIF_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
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#define _BUFC_SEQIF_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
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#define _BUFC_SEQIF_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0CORR_DEFAULT (_BUFC_SEQIF_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0NWA (0x1UL << 4) /**< Buffer 0 Not Word-Aligned */
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#define _BUFC_SEQIF_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
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#define _BUFC_SEQIF_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
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#define _BUFC_SEQIF_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF0NWA_DEFAULT (_BUFC_SEQIF_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1OF (0x1UL << 8) /**< Buffer 1 Overflow */
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#define _BUFC_SEQIF_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
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#define _BUFC_SEQIF_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
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#define _BUFC_SEQIF_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1OF_DEFAULT (_BUFC_SEQIF_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1UF (0x1UL << 9) /**< Buffer 1 Underflow */
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#define _BUFC_SEQIF_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
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#define _BUFC_SEQIF_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
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#define _BUFC_SEQIF_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1UF_DEFAULT (_BUFC_SEQIF_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1THR (0x1UL << 10) /**< Buffer 1 Threshold Event */
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#define _BUFC_SEQIF_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
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#define _BUFC_SEQIF_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
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#define _BUFC_SEQIF_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1THR_DEFAULT (_BUFC_SEQIF_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1CORR (0x1UL << 11) /**< Buffer 1 Corrupt */
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#define _BUFC_SEQIF_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
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#define _BUFC_SEQIF_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
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#define _BUFC_SEQIF_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1CORR_DEFAULT (_BUFC_SEQIF_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1NWA (0x1UL << 12) /**< Buffer 1 Not Word-Aligned */
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#define _BUFC_SEQIF_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
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#define _BUFC_SEQIF_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
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#define _BUFC_SEQIF_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF1NWA_DEFAULT (_BUFC_SEQIF_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2OF (0x1UL << 16) /**< Buffer 2 Overflow */
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#define _BUFC_SEQIF_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
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#define _BUFC_SEQIF_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
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#define _BUFC_SEQIF_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2OF_DEFAULT (_BUFC_SEQIF_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2UF (0x1UL << 17) /**< Buffer 2 Underflow */
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#define _BUFC_SEQIF_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
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#define _BUFC_SEQIF_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
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#define _BUFC_SEQIF_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2UF_DEFAULT (_BUFC_SEQIF_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2THR (0x1UL << 18) /**< Buffer 2 Threshold Event */
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#define _BUFC_SEQIF_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
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#define _BUFC_SEQIF_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
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#define _BUFC_SEQIF_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2THR_DEFAULT (_BUFC_SEQIF_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2CORR (0x1UL << 19) /**< Buffer 2 Corrupt */
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#define _BUFC_SEQIF_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
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#define _BUFC_SEQIF_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
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#define _BUFC_SEQIF_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2CORR_DEFAULT (_BUFC_SEQIF_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2NWA (0x1UL << 20) /**< Buffer 2 Not Word-Aligned */
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#define _BUFC_SEQIF_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
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#define _BUFC_SEQIF_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
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#define _BUFC_SEQIF_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF2NWA_DEFAULT (_BUFC_SEQIF_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3OF (0x1UL << 24) /**< Buffer 3 Overflow */
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#define _BUFC_SEQIF_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
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#define _BUFC_SEQIF_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
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#define _BUFC_SEQIF_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3OF_DEFAULT (_BUFC_SEQIF_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3UF (0x1UL << 25) /**< Buffer 3 Underflow */
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#define _BUFC_SEQIF_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
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#define _BUFC_SEQIF_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
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#define _BUFC_SEQIF_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3UF_DEFAULT (_BUFC_SEQIF_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3THR (0x1UL << 26) /**< Buffer 3 Threshold Event */
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#define _BUFC_SEQIF_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
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#define _BUFC_SEQIF_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
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#define _BUFC_SEQIF_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3THR_DEFAULT (_BUFC_SEQIF_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3CORR (0x1UL << 27) /**< Buffer 3 Corrupt */
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#define _BUFC_SEQIF_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
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#define _BUFC_SEQIF_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
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#define _BUFC_SEQIF_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3CORR_DEFAULT (_BUFC_SEQIF_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3NWA (0x1UL << 28) /**< Buffer 3 Not Word-Aligned */
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#define _BUFC_SEQIF_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
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#define _BUFC_SEQIF_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
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#define _BUFC_SEQIF_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUF3NWA_DEFAULT (_BUFC_SEQIF_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUSERROR (0x1UL << 31) /**< Bus Error */
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#define _BUFC_SEQIF_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
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#define _BUFC_SEQIF_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
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#define _BUFC_SEQIF_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIF */
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#define BUFC_SEQIF_BUSERROR_DEFAULT (_BUFC_SEQIF_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIF */
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/* Bit fields for BUFC SEQIEN */
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#define _BUFC_SEQIEN_RESETVALUE 0x00000000UL /**< Default value for BUFC_SEQIEN */
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#define _BUFC_SEQIEN_MASK 0x9F1F1F1FUL /**< Mask for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0OF (0x1UL << 0) /**< BUF0OF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF0OF_SHIFT 0 /**< Shift value for BUFC_BUF0OF */
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#define _BUFC_SEQIEN_BUF0OF_MASK 0x1UL /**< Bit mask for BUFC_BUF0OF */
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#define _BUFC_SEQIEN_BUF0OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0OF_DEFAULT (_BUFC_SEQIEN_BUF0OF_DEFAULT << 0) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0UF (0x1UL << 1) /**< BUF0UF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF0UF_SHIFT 1 /**< Shift value for BUFC_BUF0UF */
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#define _BUFC_SEQIEN_BUF0UF_MASK 0x2UL /**< Bit mask for BUFC_BUF0UF */
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#define _BUFC_SEQIEN_BUF0UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0UF_DEFAULT (_BUFC_SEQIEN_BUF0UF_DEFAULT << 1) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0THR (0x1UL << 2) /**< BUF0THR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF0THR_SHIFT 2 /**< Shift value for BUFC_BUF0THR */
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#define _BUFC_SEQIEN_BUF0THR_MASK 0x4UL /**< Bit mask for BUFC_BUF0THR */
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#define _BUFC_SEQIEN_BUF0THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0THR_DEFAULT (_BUFC_SEQIEN_BUF0THR_DEFAULT << 2) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0CORR (0x1UL << 3) /**< BUF0CORR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF0CORR_SHIFT 3 /**< Shift value for BUFC_BUF0CORR */
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#define _BUFC_SEQIEN_BUF0CORR_MASK 0x8UL /**< Bit mask for BUFC_BUF0CORR */
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#define _BUFC_SEQIEN_BUF0CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0CORR_DEFAULT (_BUFC_SEQIEN_BUF0CORR_DEFAULT << 3) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0NWA (0x1UL << 4) /**< BUF0NWA Interrupt Enable */
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#define _BUFC_SEQIEN_BUF0NWA_SHIFT 4 /**< Shift value for BUFC_BUF0NWA */
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#define _BUFC_SEQIEN_BUF0NWA_MASK 0x10UL /**< Bit mask for BUFC_BUF0NWA */
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#define _BUFC_SEQIEN_BUF0NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF0NWA_DEFAULT (_BUFC_SEQIEN_BUF0NWA_DEFAULT << 4) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1OF (0x1UL << 8) /**< BUF1OF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF1OF_SHIFT 8 /**< Shift value for BUFC_BUF1OF */
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#define _BUFC_SEQIEN_BUF1OF_MASK 0x100UL /**< Bit mask for BUFC_BUF1OF */
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#define _BUFC_SEQIEN_BUF1OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1OF_DEFAULT (_BUFC_SEQIEN_BUF1OF_DEFAULT << 8) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1UF (0x1UL << 9) /**< BUF1UF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF1UF_SHIFT 9 /**< Shift value for BUFC_BUF1UF */
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#define _BUFC_SEQIEN_BUF1UF_MASK 0x200UL /**< Bit mask for BUFC_BUF1UF */
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#define _BUFC_SEQIEN_BUF1UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1UF_DEFAULT (_BUFC_SEQIEN_BUF1UF_DEFAULT << 9) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1THR (0x1UL << 10) /**< BUF1THR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF1THR_SHIFT 10 /**< Shift value for BUFC_BUF1THR */
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#define _BUFC_SEQIEN_BUF1THR_MASK 0x400UL /**< Bit mask for BUFC_BUF1THR */
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#define _BUFC_SEQIEN_BUF1THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1THR_DEFAULT (_BUFC_SEQIEN_BUF1THR_DEFAULT << 10) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1CORR (0x1UL << 11) /**< BUF1CORR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF1CORR_SHIFT 11 /**< Shift value for BUFC_BUF1CORR */
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#define _BUFC_SEQIEN_BUF1CORR_MASK 0x800UL /**< Bit mask for BUFC_BUF1CORR */
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#define _BUFC_SEQIEN_BUF1CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1CORR_DEFAULT (_BUFC_SEQIEN_BUF1CORR_DEFAULT << 11) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1NWA (0x1UL << 12) /**< BUF1NWA Interrupt Enable */
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#define _BUFC_SEQIEN_BUF1NWA_SHIFT 12 /**< Shift value for BUFC_BUF1NWA */
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#define _BUFC_SEQIEN_BUF1NWA_MASK 0x1000UL /**< Bit mask for BUFC_BUF1NWA */
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#define _BUFC_SEQIEN_BUF1NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF1NWA_DEFAULT (_BUFC_SEQIEN_BUF1NWA_DEFAULT << 12) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2OF (0x1UL << 16) /**< BUF2OF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF2OF_SHIFT 16 /**< Shift value for BUFC_BUF2OF */
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#define _BUFC_SEQIEN_BUF2OF_MASK 0x10000UL /**< Bit mask for BUFC_BUF2OF */
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#define _BUFC_SEQIEN_BUF2OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2OF_DEFAULT (_BUFC_SEQIEN_BUF2OF_DEFAULT << 16) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2UF (0x1UL << 17) /**< BUF2UF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF2UF_SHIFT 17 /**< Shift value for BUFC_BUF2UF */
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#define _BUFC_SEQIEN_BUF2UF_MASK 0x20000UL /**< Bit mask for BUFC_BUF2UF */
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#define _BUFC_SEQIEN_BUF2UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2UF_DEFAULT (_BUFC_SEQIEN_BUF2UF_DEFAULT << 17) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2THR (0x1UL << 18) /**< BUF2THR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF2THR_SHIFT 18 /**< Shift value for BUFC_BUF2THR */
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#define _BUFC_SEQIEN_BUF2THR_MASK 0x40000UL /**< Bit mask for BUFC_BUF2THR */
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#define _BUFC_SEQIEN_BUF2THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2THR_DEFAULT (_BUFC_SEQIEN_BUF2THR_DEFAULT << 18) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2CORR (0x1UL << 19) /**< BUF2CORR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF2CORR_SHIFT 19 /**< Shift value for BUFC_BUF2CORR */
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#define _BUFC_SEQIEN_BUF2CORR_MASK 0x80000UL /**< Bit mask for BUFC_BUF2CORR */
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#define _BUFC_SEQIEN_BUF2CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2CORR_DEFAULT (_BUFC_SEQIEN_BUF2CORR_DEFAULT << 19) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2NWA (0x1UL << 20) /**< BUF2NWA Interrupt Enable */
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#define _BUFC_SEQIEN_BUF2NWA_SHIFT 20 /**< Shift value for BUFC_BUF2NWA */
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#define _BUFC_SEQIEN_BUF2NWA_MASK 0x100000UL /**< Bit mask for BUFC_BUF2NWA */
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#define _BUFC_SEQIEN_BUF2NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF2NWA_DEFAULT (_BUFC_SEQIEN_BUF2NWA_DEFAULT << 20) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3OF (0x1UL << 24) /**< BUF3OF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF3OF_SHIFT 24 /**< Shift value for BUFC_BUF3OF */
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#define _BUFC_SEQIEN_BUF3OF_MASK 0x1000000UL /**< Bit mask for BUFC_BUF3OF */
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#define _BUFC_SEQIEN_BUF3OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3OF_DEFAULT (_BUFC_SEQIEN_BUF3OF_DEFAULT << 24) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3UF (0x1UL << 25) /**< BUF3UF Interrupt Enable */
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#define _BUFC_SEQIEN_BUF3UF_SHIFT 25 /**< Shift value for BUFC_BUF3UF */
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#define _BUFC_SEQIEN_BUF3UF_MASK 0x2000000UL /**< Bit mask for BUFC_BUF3UF */
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#define _BUFC_SEQIEN_BUF3UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3UF_DEFAULT (_BUFC_SEQIEN_BUF3UF_DEFAULT << 25) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3THR (0x1UL << 26) /**< BUF3THR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF3THR_SHIFT 26 /**< Shift value for BUFC_BUF3THR */
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#define _BUFC_SEQIEN_BUF3THR_MASK 0x4000000UL /**< Bit mask for BUFC_BUF3THR */
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#define _BUFC_SEQIEN_BUF3THR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3THR_DEFAULT (_BUFC_SEQIEN_BUF3THR_DEFAULT << 26) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3CORR (0x1UL << 27) /**< BUF3CORR Interrupt Enable */
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#define _BUFC_SEQIEN_BUF3CORR_SHIFT 27 /**< Shift value for BUFC_BUF3CORR */
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#define _BUFC_SEQIEN_BUF3CORR_MASK 0x8000000UL /**< Bit mask for BUFC_BUF3CORR */
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#define _BUFC_SEQIEN_BUF3CORR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3CORR_DEFAULT (_BUFC_SEQIEN_BUF3CORR_DEFAULT << 27) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3NWA (0x1UL << 28) /**< BUF3NWA Interrupt Enable */
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#define _BUFC_SEQIEN_BUF3NWA_SHIFT 28 /**< Shift value for BUFC_BUF3NWA */
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#define _BUFC_SEQIEN_BUF3NWA_MASK 0x10000000UL /**< Bit mask for BUFC_BUF3NWA */
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#define _BUFC_SEQIEN_BUF3NWA_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUF3NWA_DEFAULT (_BUFC_SEQIEN_BUF3NWA_DEFAULT << 28) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUSERROR (0x1UL << 31) /**< BUSERROR Interrupt Enable */
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#define _BUFC_SEQIEN_BUSERROR_SHIFT 31 /**< Shift value for BUFC_BUSERROR */
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#define _BUFC_SEQIEN_BUSERROR_MASK 0x80000000UL /**< Bit mask for BUFC_BUSERROR */
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#define _BUFC_SEQIEN_BUSERROR_DEFAULT 0x00000000UL /**< Mode DEFAULT for BUFC_SEQIEN */
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#define BUFC_SEQIEN_BUSERROR_DEFAULT (_BUFC_SEQIEN_BUSERROR_DEFAULT << 31) /**< Shifted mode DEFAULT for BUFC_SEQIEN */
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/** @} End of group BGM22_BUFC_BitFields */
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/** @} End of group BGM22_BUFC */
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/** @} End of group Parts */
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#endif /* BGM22_BUFC_H */
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